.#' VERILOG°" $1ý " $1þ 3 create_syntax_tableý" //  " 37 " $1þ - define_syntaxý# ([{# )]}" 40 " $1þ - define_syntaxý" 34" 34 " $1þ - define_syntaxý" 36" 92 " $1þ - define_syntaxý" 96" 92 " $1þ - define_syntaxý* 0-9a-zA-Z_# 119 " $1þ
 - define_syntaxý/ -+0-9a-FA-F.xXL" 48 " $1þ - define_syntaxý( ,;.?:=<>" 44 " $1þ - define_syntaxý" 35" 35 " $1þ - define_syntaxý, %-+/&*<>|!~^" 43 " $1þ - define_syntaxý " $1! 8þ 0 set_syntax_flagsý " $14 IFINISOFTOifinisofto! 2þ
 / define_keywordsPý " $1M ANDENDFORMAXMINOUTUSEandendformaxminoutreguse! 3þ / define_keywordsPý " $1` CASEELSELOOPPORTTASKTHENWAITWIREcaseelseloopporttaskthenwaitwire! 4þ / define_keywordsPý " $1
W BEGINEVENTINOUTINPUTINOUTWHILEbegineventinoutinputwhile! 5þ / define_keywordsPý " $1’ ASSIGNBUFFERDOWNTOENTITYMODULEREPEATRETURNSIGNALASSIGNalwaysassignbufferdowntoentitymoduleoutputrepeatreturnsignal! 6þ / define_keywordsPý " $1
ž DEFAULTENDCASEENDTASKFOREVERINITIALINTEGERNEGEDGEPOSEDGESPECIFYdefaultendcaseendtaskforeverinitialintegernegedgeposedgespecify! 7þ / define_keywordsPý " $1@ CONSTANTFUNCTIONconstantfunction! 8þ / define_keywordsPý " $1
V ENDMODULEPARAMETERSPECPARAMendmoduleparameterspecparam! 9þ / define_keywordsPý " $14 ENDSPECIFYendspecify" 10þ / define_keywordsP,* $ kmap+' VERILOG°$ kmapý $ kmap" 40þ ( set_modeý $ kmapþ 0 use_syntax_tableý1 verilog_mode_hookþ
 . run_mode_hooksy, verilog_mode