main module TEST32L
	use textio
	declare
		A : static 32 bit integer 
		B : static 32 bit integer 
		A16 : static 16 bit integer 
		B16 : static 16  bit integer 
	enddeclare

	B := -1
	A := 0
	B16 := -1
	A16 := 0

	out_string ( tty,"A is:")
	out_integer (tty,A)
	Out_record ( tty)

	out_string ( tty,"B is:")
	out_integer (tty,B)
	Out_record ( tty)

	
	if A > B do
		tty_line( " I think that A is greater than B" )
	otherwise 
		tty_line( " I think that A is not greater than B" )
	endif
	
	if A < B do
		tty_line( " I think that A is less than B" )
	otherwise 
		tty_line( " I think that A is not less than B" )
	endif

	if A >= B do
		tty_line( " I think that A is greater than or = B " )
	otherwise 
		tty_line( " I think that A is not greater than or = B" )
	endif

	if A <= B do
		tty_line( " I think that A is less than or =B" )
	otherwise 
		tty_line( " I think that A is not less than or = B" )
	endif

	if A = B do
		tty_line( " I think that A=B" )
	otherwise 
		tty_line( " I think that A not = B" )
	endif

	if A <> B do
		tty_line( " I think that A is not equal B" )
	otherwise 
		tty_line( " I think that A is not not equal B" )
	endif
//-------------------------------------	
	if A16> B16 do
		tty_line( " I think that A16is greater than  B16" )
	otherwise 
		tty_line( " I think that A16is not greater than  B16" )
	endif
	
	if A16<  B16 do
		tty_line( " I think that A16is less than  B16" )
	otherwise 
		tty_line( " I think that A16is not less than  B16" )
	endif

	if A16>=  B16 do
		tty_line( " I think that A16is greater than or =  B16 " )
	otherwise 
		tty_line( " I think that A16is not greater than or =  B16" )
	endif

	if A16<=  B16 do
		tty_line( " I think that A16is less than or = B16" )
	otherwise 
		tty_line( " I think that A16is not less than or =  B16" )
	endif

	if A16=  B16 do
		tty_line( " I think that A= B16" )
	otherwise 
		tty_line( " I think that A16not =  B16" )
	endif

	if A16<>  B16 do
		tty_line( " I think that A16is not equal  B16" )
	otherwise 
		tty_line( " I think that A16is not not equal  B16" )
	endif
	
endmodule