; ********************************************************************************************************************************
;  Created: 17-APR-1997 22:18:41 by OpenVMS SDL EV1-52     
;  Source:  14-FEB-1996 10:54:39 $64$DUA2530:[SCSI.SRC]ISP1020DEF.SDL;1 
; ********************************************************************************************************************************
 
	.MACRO	$ISP1020DEF,$GBL
	$DEFINI	ISP1020,$GBL
	.SYMBOL_ALIGNMENT QUAD
$EQU	ISP$S_DATA_SEG	8
$EQU	ISP$PS_BASE_ADDRESS	0       ;  Segment base address
$EQU	ISP$L_BYTE_COUNT	4       ;  Segment length in bytes
$EQU	ISP$K_TY_COMMAND	1       ;  Command
$EQU	ISP$K_TY_CONTINUATION	2       ;  Continuation
$EQU	ISP$K_TY_STATUS	3               ;  Status
$EQU	ISP$K_TY_MARKER	4               ;  Marker
$EQU	ISP$K_TY_EXTENDED	5       ;  Extended command
$EQU	ISP$K_TY_ATIO	6               ;  Accept target IO
$EQU	ISP$K_TY_CTIO	7               ;  Continue target IO
$EQU	ISP$K_TY_RESERVED	8       ;  Maybe extended sense message
$EQU	ISP$K_TY_COMMAND_64	9       ;  64bit Command
$EQU	ISP$K_TY_CONTINUATION_64	10 ;  64 bit continuation
$EQU	ISP$K_TY_ENABLE_LUN	11      ;  enable lun
$EQU	ISP$K_TY_MODIFY_LUN	12      ;  modify lun
$EQU	ISP$K_TY_NOTIFY	13              ;  immediate notify
$EQU	ISP$K_TY_NOTIFY_ACK	14      ;  notify acknowledge
$EQU	ISP$K_TY_CTIO_64	15      ;  64 bit CTIO
$EQU	ISP$M_HF_CONTINUATION	<^X1>
$EQU	ISP$M_HF_FULL	<^X2>
$EQU	ISP$M_HF_BADHEADER	<^X4>
$EQU	ISP$M_HF_BADPAYLOAD	<^X8>
$EQU	ISP$M_CF_NO_DISCONNECT	<^X1>
$EQU	ISP$M_CF_HEAD	<^X2>
$EQU	ISP$M_CF_ORDERED	<^X4>
$EQU	ISP$M_CF_SIMPLE	<^X8>
$EQU	ISP$M_CF_TARGET_ROUTINE	<^X10>
$EQU	ISP$M_CF_DATA_DIRECTION	<^X60>
$EQU	ISP$K_DD_NOT_XFR	0       ;  Not a data transfer
$EQU	ISP$K_DD_READ	1               ;  Read (Data in)
$EQU	ISP$K_DD_WRITE	2               ;  Write (Data out)
$EQU	ISP$K_DD_TARGET	3               ;  Direction determined by target
$EQU	ISP$K_MD_TARGET_LUN	0       ;  Synchronize specified LUN at target device
$EQU	ISP$K_MD_TARGET_ALL	1       ;  Synchronize all LUNs at target device
$EQU	ISP$K_MD_ALL	2               ;  Synchronize all LUNs at all devices
$EQU	ISP$K_CS_COMPLETE	0       ;  Normal completion
$EQU	ISP$K_CS_INCOMPLETE	1       ;  Abnormal transport state
$EQU	ISP$K_CS_DMA	2               ;  DMA direction error
$EQU	ISP$K_CS_TRANSPORT	3       ;  Unspecified transport error
$EQU	ISP$K_CS_RESET	4               ;  SCSI bus reset
$EQU	ISP$K_CS_ABORTED	5       ;  Driver aborted command
$EQU	ISP$K_CS_TIMEOUT	6       ;  Transport timed out
$EQU	ISP$K_CS_DATA_OVERRUN	7       ;  Data overrun, excess discarded
$EQU	ISP$K_CS_COMMAND_OVERRUN	8 ;  Command data UNDERrun, zeros supplied
$EQU	ISP$K_CS_STATUS_OVERRUN	9       ;  Excess status bytes, ignored
$EQU	ISP$K_CS_BAD_MESSAGE	10      ;  No command complete after status phase
$EQU	ISP$K_CS_NO_MESSAGE_OUT	11      ;  No Message Out phase seen after select
$EQU	ISP$K_CS_EXTENDED_ID_FAIL	12 ;  Extended Id message failure
$EQU	ISP$K_CS_IDE_FAIL	13      ;  IDE message failure
$EQU	ISP$K_CS_ABORT_FAIL	14      ;  Abort message failure
$EQU	ISP$K_CS_REJECT_FAIL	15      ;  Reject message failure
$EQU	ISP$K_CS_NOP_FAIL	16      ;  NOP message failure
$EQU	ISP$K_CS_PARITY_ERROR_FAIL	17 ;  Parity error message failure
$EQU	ISP$K_CS_DEVICE_RESET_FAIL	18 ;  Device reset message failure
$EQU	ISP$K_CS_IDENTIFY_FAIL	19      ;  Identify message failure
$EQU	ISP$K_CS_UNEXP_BUS_FREE	20      ;  Unexpected bus free during command
$EQU	ISP$K_CS_DATA_UNDERRUN	21      ;  Data underrun, zeros supplied
$EQU	ISP$K_CS_COMMAND_UNDERRUN	22 ;  Command underrun
$EQU	ISP$K_CS_MESSAGE_UNDERRUN	23 ;  Message underrun
$EQU	ISP$K_CS_Q_NO_DISCONNECT	24 ;  Q'd transaction w/o disconnect privilege
$EQU	ISP$K_CS_Q_TARGET_ROUTINE	25 ;  Q'd transaction specified target routine
$EQU	ISP$K_CS_Q_QING_DISABLED	26 ;  Q'd transaction while queueing disabled
$EQU	ISP$M_SF_GOT_BUS	<^X100>
$EQU	ISP$M_SF_GOT_TARGET	<^X200>
$EQU	ISP$M_SF_SENT_COMMAND	<^X400>
$EQU	ISP$M_SF_XFRD_DATA	<^X800>
$EQU	ISP$M_SF_GOT_STATUS	<^X1000>
$EQU	ISP$M_SF_GOT_SENSE	<^X2000>
$EQU	ISP$M_SF_XFR_COMPLETE	<^X4000>
$EQU	ISP$M_OF_DISCONNECT	<^X1>
$EQU	ISP$M_OF_SYNCHRONOUS	<^X2>
$EQU	ISP$M_OF_PARITY_ERROR	<^X4>
$EQU	ISP$M_OF_BUS_RESET	<^X8>
$EQU	ISP$M_OF_DEVICE_RESET	<^X10>
$EQU	ISP$M_OF_ABORTED	<^X20>
$EQU	ISP$M_OF_TIMEOUT	<^X40>
$EQU	ISP$M_OF_NEGOTIATED	<^X80>
$EQU	ISP$M_RESERVED_EL_3	<^X1>
$EQU	ISP$M_TAGGED_QUEUE_ENABLE	2
$EQU	ISP$M_DISABLE_SENDING_SDP	16777216
$EQU	ISP$M_DISCONNECT_MANDATORY	<^X40000000>
$EQU	ISP$M_RESERVED_8	<^X1>
$EQU	ISP$M_TAGGED_QUEUE_ENABLE	<^X2>
$EQU	ISP$M_AUTOSENSE_VALID	128
$EQU	ISP$K_INVALID_REQUEST	6       ;  invalid request
$EQU	ISP$K_CAP_NOT_AVAIL	22      ;  capacity not available
$EQU	ISP$K_MESSAGE_RECEIVED	54      ;  message received
$EQU	ISP$K_NEXUS_NOT_ESTABLISHED	59 ;  nexus not setablished
$EQU	ISP$K_REQUEST_COMPLETED_OK	1 ;  request completed without error
$EQU	ISP$M_AUTOSENSE_VALID	<^X80>
$EQU	ISP$M_RESET_CLEARED	<^X80>
$EQU	ISP$M_RESERVED_M0	<^X1>
$EQU	ISP$M_TAGGED_QUEUE_ENABLED	<^X2>
$EQU	ISP$M_ATIO_DISCONNECTS_DISABLED	<^X8000>
$EQU	ISP$M_RESERVED_L	<^X1>
$EQU	ISP$M_RESERVED_K0	<^X1>
$EQU	ISP$M_TAG_ENABLE	<^X2>
$EQU	ISP$M_CTIO_DISCONNECTS_DISABLED	<^X8000>
$EQU	ISP$M_DISABLE_SENDING_SDP	<^X1000000>
$EQU	ISP$M_RESERVED_K25	<^X2000000>
$EQU	ISP$M_SEND_RESTORE_POINTERS	<^X4000000>
$EQU	ISP$M_SEND_SCSI_STATUS	<^X80000000>
$EQU	ISP$K_CTIO_AUTOSENSE_VALID	128 ;  autosense valid
$EQU	ISP$K_CTIO_COMPLETED_WO_ERROR	1 ;  io completed without error
$EQU	ISP$K_CTIO_ABORTED_BY_HOST	2 ;  xfer aborted by host
$EQU	ISP$K_CTIO_INVALID_REQUEST	6 ;  invalid request
$EQU	ISP$K_CTIO_PATH_INVALID	7       ;  invalid path
$EQU	ISP$K_CTIO_RESELECTION_TIMEOUT	10 ;  reselce timeout 
$EQU	ISP$K_CTIO_COMMAND_TIMEOUT	11 ;  command timeout
$EQU	ISP$K_CTIO_SCSI_BUS_RESET	14 ;  scsi bus reset 
$EQU	ISP$K_CTIO_PARITY_ERROR	15      ;  parity error 
$EQU	ISP$K_CTIO_PHASE_SEQ_ERROR	20 ;  phase sequencs error
$EQU	ISP$K_CTIO_BDR_RECEIVED	23      ;  bus device reset received
$EQU	ISP$K_CTIO_INITIATOR_DETECTED_ERR	51 ;  initiator detected error
$EQU	ISP$K_CTIO_UNACKED_EVENT_BY_HOST	53 ;  unacknowledged event by host
$EQU	ISP$M_RESERVED_J	<^X1>
$EQU	ISP$S_ISP_ENTRY	64
$EQU	ISP$B_TYPE	0               ;  Entry type
$EQU	ISP$B_COUNT	1               ;  Entry count
$EQU	ISP$B_SYSDEF_1	2               ;  Driver-defined field
$EQU	ISP$B_HEADER_FLAGS	3       ;  Entry flags
$EQU	ISP$V_HF_CONTINUATION	0       ;  Continuation entry
$EQU	ISP$V_HF_FULL	1               ;  Queue full
$EQU	ISP$V_HF_BADHEADER	2       ;  Bad header
$EQU	ISP$V_HF_BADPAYLOAD	3       ;  Bad payload
$EQU	ISP$L_HANDLE	4               ;  Command handle
$EQU	ISP$S_COMMAND_ENTRY	56
$EQU	ISP$R_COMMAND_ENTRY	8
$EQU	ISP$B_LUN	8               ;  Logical unit
$EQU	ISP$B_TARGET	9               ;  SCSI ID of target device
$EQU	ISP$W_CDB_LENGTH	10      ;  Length of CDB in bytes
$EQU	ISP$W_CONTROL_FLAGS	12      ;  Control firmware execution of command
$EQU	ISP$V_CF_NO_DISCONNECT	0       ;  Disable disconnect privilege
$EQU	ISP$V_CF_HEAD	1               ;  Head of queue tag
$EQU	ISP$V_CF_ORDERED	2       ;  Ordered queue tag
$EQU	ISP$V_CF_SIMPLE	3               ;  Simple queue tag
$EQU	ISP$V_CF_TARGET_ROUTINE	4       ;  Set target routine byte in SCSI ID
$EQU	ISP$S_CF_DATA_DIRECTION	2
$EQU	ISP$V_CF_DATA_DIRECTION	5       ;  Data direction (2 bits)
$EQU	ISP$W_RESERVED_0	14      ;  Reserved
$EQU	ISP$W_TIMEOUT	16              ;  Timeout in seconds
$EQU	ISP$W_DATA_SEG_COUNT	18      ;  Total data segments in transfer
$EQU	ISP$R_COMMAND_OVERLAY	20
$EQU	ISP$S_COMMAND_STRUCTURE	44
$EQU	ISP$R_COMMAND_STRUCTURE	20      ;  Structure for normal command
$EQU	ISP$S_CDB	12
$EQU	ISP$B_CDB	20              ;  SCSI Command Data Block
$EQU	ISP$R_DATA_SEG	32              ;  Data segments 0 - 3
$EQU	ISP$S_EXTENDED_CDB	44
$EQU	ISP$B_EXTENDED_CDB	20      ;  SCSI extended Command Data Block
$EQU	ISP$S_CONTINUATION_ENTRY	56
$EQU	ISP$R_CONTINUATION_ENTRY	8
$EQU	ISP$R_CONT_SEG	8               ;  Continuation segments 0 - 6
$EQU	ISP$S_MARKER_ENTRY	8
$EQU	ISP$R_MARKER_ENTRY	8
$EQU	ISP$B_MODIFIER	10              ;  Synchronization modifier
$EQU	ISP$B_MARKER_RESERVED_MBZ	11 ;  reserved byte must be zero
$EQU	ISP$L_MARKER_RESERVED	12      ;  reserved 
$EQU	ISP$S_STATUS_ENTRY	56
$EQU	ISP$R_STATUS_ENTRY	8
$EQU	ISP$B_SCSI_STATUS	8       ;  Status returned by target
$EQU	ISP$W_COMPLETION_STATUS	10      ;  ISP completion status
$EQU	ISP$W_BUS_STATES	12      ;  Bus states seen during transport
$EQU	ISP$V_SF_GOT_BUS	8       ;  Bus arbitration succeeded
$EQU	ISP$V_SF_GOT_TARGET	9       ;  Target selection succeeded
$EQU	ISP$V_SF_SENT_COMMAND	10      ;  CDB transfer succeeded
$EQU	ISP$V_SF_XFRD_DATA	11      ;  Data in/Data out phase transfer happened
$EQU	ISP$V_SF_GOT_STATUS	12      ;  Status phase transfer succeeded
$EQU	ISP$V_SF_GOT_SENSE	13      ;  Auto Request Sense data succeeded
$EQU	ISP$V_SF_XFR_COMPLETE	14      ;  Data in/Data out phase transfer succeeded
$EQU	ISP$W_BUS_OPERATION	14      ;  Bus operating conditions seen during transport
$EQU	ISP$V_OF_DISCONNECT	0       ;  A disconnect occurred during transport
$EQU	ISP$V_OF_SYNCHRONOUS	1       ;  All data phase transfers were synchronous
$EQU	ISP$V_OF_PARITY_ERROR	2       ;  SCSI bus parity error occurred
$EQU	ISP$V_OF_BUS_RESET	3       ;  SCSI bus reset occurred during transport
$EQU	ISP$V_OF_DEVICE_RESET	4       ;  Device reset message seen by firmware
$EQU	ISP$V_OF_ABORTED	5       ;  Command aborted by host
$EQU	ISP$V_OF_TIMEOUT	6       ;  Command timed out
$EQU	ISP$V_OF_NEGOTIATED	7       ;  Synch or wide data transfer were negotiated
$EQU	ISP$W_REMAINING_TIME	16      ;  Time remaining before timeout
$EQU	ISP$W_SENSE_DATA_LENGTH	18      ;  Length of request sense data (bytes)
$EQU	ISP$L_BYTES_NOT_XFRD	20      ;  Bytes requested but not transferred
$EQU	ISP$S_SENSE_DATA	32
$EQU	ISP$B_SENSE_DATA	32      ;  Buffer returned by auto Request Sense
$EQU	ISP$S_ENABLE_LUN_ENTRY	56
$EQU	ISP$R_ENABLE_LUN_ENTRY	8       ;  Enable Lun entry
$EQU	ISP$B_LUN	8               ;  Lun value
$EQU	ISP$S_RESERVED_EL_2	3
$EQU	ISP$B_RESERVED_EL_2	9       ;  reserved
$EQU	ISP$L_ENABLE_LUN_FLAGS	12      ;  longword field
$EQU	ISP$V_RESERVED_EL_3	0       ;  reserved
$EQU	ISP$V_TAGGED_QUEUE_ENABLE	1 ;  tagged queue enable
$EQU	ISP$V_DISABLE_SENDING_SDP	24 ;  disable save data pointers
$EQU	ISP$V_DISCONNECT_MANDATORY	30 ;  require disconnect enable.
$EQU	ISP$B_STATUS	16              ;  status byte
$EQU	ISP$B_RESERVED_EL_6	17      ;  reserved
$EQU	ISP$B_COMMAND_COUNT	18      ;  command count (max commands)
$EQU	ISP$B_NOTIFY_COUNT	19      ;  notify count (max notify)
$EQU	ISP$B_GROUP_6_COUNT	20      ;  size of group 6 commands
$EQU	ISP$B_GROUP_7_COUNT	21      ;  size of group 7 commands
$EQU	ISP$W_ENABLE_LUN_TIMEOUT	22 ;  timeout
$EQU	ISP$S_RESERVED_EL_7	40
$EQU	ISP$W_RESERVED_EL_7	24      ;  reserved
$EQU	ISP$S_NOTIFY_ENTRY	56
$EQU	ISP$R_NOTIFY_ENTRY	8       ;  modify lun structure
$EQU	ISP$B_LUN	8               ;  lub value
$EQU	ISP$B_INITIATOR_ID	9       ;  initiator id value
$EQU	ISP$B_RESERVED	10              ;  reserved 
$EQU	ISP$B_TARGET_ID	11              ;  target id value
$EQU	ISP$L_NOTIFY_FLAGS	12      ;  longword of flags
$EQU	ISP$V_RESERVED_8	0       ;  reserved
$EQU	ISP$V_TAGGED_QUEUE_ENABLE	1 ;  enable tagged operation
$EQU	ISP$B_NOTIFY_STATUS	16      ;  byte field
$EQU	ISP$S_STATUS	7
$EQU	ISP$V_STATUS	0               ;  status value
$EQU	ISP$V_AUTOSENSE_VALID	7       ;  autosense valid bit
$EQU	ISP$B_RESERVED_B	17      ;  reserved
$EQU	ISP$B_TAG_VALUE	18              ;  tag value
$EQU	ISP$B_TAG_TYPE	19              ;  tag type
$EQU	ISP$W_SEQUENCE_ID	20      ;  sequence #
$EQU	ISP$S_SCSI_MESSAGE	8
$EQU	ISP$B_SCSI_MESSAGE	22      ;  scsi message buffer
$EQU	ISP$S_RESERVED_C	16
$EQU	ISP$W_RESERVED_C	30      ;  reserved
$EQU	ISP$S_NOTIFY_SENSE_DATA	18
$EQU	ISP$B_NOTIFY_SENSE_DATA	46      ;  sense data
$EQU	ISP$S_NOTIFY_ACK_ENTRY	56
$EQU	ISP$R_NOTIFY_ACK_ENTRY	8       ;  notify acknowldge structure
$EQU	ISP$B_LUN	8               ;  lun byte
$EQU	ISP$B_INITIATOR_ID	9       ;  initiator id
$EQU	ISP$B_RESERVED	10              ;  reserved
$EQU	ISP$B_TARGET_ID	11              ;  target id
$EQU	ISP$L_NOTIFY_FLAGS	12      ;  longword value
$EQU	ISP$B_NOTIFY_STATUS	16      ;  byte field
$EQU	ISP$S_STATUS	7
$EQU	ISP$V_STATUS	0               ;  status value
$EQU	ISP$V_AUTOSENSE_VALID	7       ;  autosense valid
$EQU	ISP$B_EVENT	17              ;  byte field
$EQU	ISP$V_RESET_CLEARED	7       ;  reset_cleared
$EQU	ISP$W_SEQUENCE_ID	18      ;  sequence #
$EQU	ISP$S_RESERVED_E	44
$EQU	ISP$B_RESERVED_E	20      ;  reserved
$EQU	ISP$S_ACCEPT_TARGET_ENTRY	56
$EQU	ISP$R_ACCEPT_TARGET_ENTRY	8 ;  accept target io (atio)
$EQU	ISP$B_LUN	8               ;  lun
$EQU	ISP$B_INITIATOR_ID	9       ;  initiator id
$EQU	ISP$B_CDB_LEN	10              ;  cdb length
$EQU	ISP$B_TARGET_ID	11              ;  target id 
$EQU	ISP$L_ATIO_FLAGS	12      ;  longword field
$EQU	ISP$V_RESERVED_M0	0       ;  reserved
$EQU	ISP$V_TAGGED_QUEUE_ENABLED	1 ;  tagged queue enabled
$EQU	ISP$S_RESERVED_M2	13
$EQU	ISP$V_RESERVED_M2	2       ;  reserved
$EQU	ISP$V_ATIO_DISCONNECTS_DISABLED	15 ;  auto disconnext_disabled
$EQU	ISP$B_ATIO_STATUS	16      ;  byte field
$EQU	ISP$V_RESERVED_L	0       ;  reserved no statuses defined
$EQU	ISP$B_ATIO_SCSI_STATUS	17      ;  scsi status
$EQU	ISP$B_TAG_VALUE	18              ;  tag values
$EQU	ISP$B_TAG_TYPE	19              ;  tag type
$EQU	ISP$S_CDB	26
$EQU	ISP$B_CDB	20              ;  command 
$EQU	ISP$S_ATIO_SENSE_DATA	18
$EQU	ISP$B_ATIO_SENSE_DATA	46      ;  autosense data
$EQU	ISP$S_CONTINUE_TARGET_ENTRY	56
$EQU	ISP$R_CONTINUE_TARGET_ENTRY	8 ;  continue target io (ctio)
$EQU	ISP$B_LUN	8               ;  lun
$EQU	ISP$B_INITIATOR_ID	9       ;  initiator id
$EQU	ISP$B_CDB_LEN	10              ;  cdb length
$EQU	ISP$B_TARGET_ID	11              ;  target id
$EQU	ISP$L_CTIO_FLAGS	12      ;  longword field
$EQU	ISP$V_RESERVED_K0	0       ;  reserved
$EQU	ISP$V_TAG_ENABLE	1       ;  enable tagged operations
$EQU	ISP$S_RESERVED_K2	4
$EQU	ISP$V_RESERVED_K2	2       ;  reserved
$EQU	ISP$S_DATA_DIRECTION	2
$EQU	ISP$V_DATA_DIRECTION	6       ;  data direction (see command entry)
$EQU	ISP$S_RESERVED_K8	7
$EQU	ISP$V_RESERVED_K8	8       ;  reserved
$EQU	ISP$V_CTIO_DISCONNECTS_DISABLED	15 ;  disable disconnects
$EQU	ISP$S_RESERVED_K16	8
$EQU	ISP$V_RESERVED_K16	16      ;  reserved
$EQU	ISP$V_DISABLE_SENDING_SDP	24 ;  disable save data pointers
$EQU	ISP$V_RESERVED_K25	25      ;  reserved
$EQU	ISP$V_SEND_RESTORE_POINTERS	26 ;  send restore pointers
$EQU	ISP$S_RESERVED_K_27	4
$EQU	ISP$V_RESERVED_K_27	27      ;  reserved
$EQU	ISP$V_SEND_SCSI_STATUS	31      ;  send scsi status
$EQU	ISP$B_CTIO_STATUS	16
$EQU	ISP$V_RESERVED_J	0       ;  reserved
$EQU	ISP$B_CTIO_SCSI_STATUS	17      ;  scsi status
$EQU	ISP$B_TAG_VALUE	18              ;  tag value
$EQU	ISP$B_TAG_TYPE	19              ;  tag type
$EQU	ISP$L_XFER_LENGTH	20      ;  transfer length
$EQU	ISP$L_RESIDUAL_XFER_LEN	24      ;  residual data
$EQU	ISP$W_CTIO_TIMEOUT	28      ;  ctio timeout
$EQU	ISP$W_CTIO_DATA_SEG_COUNT	30 ;  data segment count
$EQU	ISP$R_CTIO_DATA_SEG	32      ;  Data segments 0 - 3
$EQU	ISP$S_MODIFY_LUN	56
$EQU	ISP$R_MODIFY_LUN	8       ;  modify lun structure
$EQU	ISP$B_LUN	8               ;  lun value
$EQU	ISP$B_RESERVED_E	9       ;  reserved
$EQU	ISP$B_OPERATORS	10              ;  operators
$EQU	ISP$B_RESERVED_F	11      ;  reserved
$EQU	ISP$L_FLAGS	12              ;  flags
$EQU	ISP$B_STATUS	16              ;  status
$EQU	ISP$B_RESERVED_G	17      ;  reserved
$EQU	ISP$B_COMMAND_COUNT	18      ;  command count
$EQU	ISP$B_NOTIFY_COUNT	19      ;  notify count
$EQU	ISP$W_RESERVED_H	20      ;  reserved
$EQU	ISP$W_MODIFY_LUN_TIMEOUT	22 ;  modify lun timeout
$EQU	ISP$S_RESERVED_I	40
$EQU	ISP$B_RESERVED_I	24      ;  reserved
$EQU	ISP$K_ENTRY_LTH	64              ;  Length of queue entry
$EQU	ISP$M_CONFIG_1_FIFO_THRESH	<^X3>
$EQU	ISP$K_FIFO_8	0               ;  Fill/empty at 8 bytes
$EQU	ISP$K_FIFO_16	1               ;  Fill/empty at 16 bytes
$EQU	ISP$K_FIFO_32	2               ;  Fill/empty at 32 bytes
$EQU	ISP$K_FIFO_64	3               ;  Fill/empty at 64 bytes
$EQU	ISP$M_CONFIG_1_BURST_ENABLE	<^X4>
$EQU	ISP$M_CONFIG_1_SEL_SXP_REGS	<^X8>
$EQU	ISP$M_ICR_SOFT_RESET	<^X1>
$EQU	ISP$M_ICR_ALL_INT_ENB	<^X2>
$EQU	ISP$M_ICR_RISC_INT_ENB	<^X4>
$EQU	ISP$M_ICR_SXP_INT_ENB	<^X8>
$EQU	ISP$M_ICR_CMD_INT_ENB	<^X10>
$EQU	ISP$M_ICR_DATA_INT_ENB	<^X20>
$EQU	ISP$M_ISR_ALL_INT	<^X2>
$EQU	ISP$M_ISR_RISC_INT	<^X4>
$EQU	ISP$M_ISR_SXP_INT	<^X8>
$EQU	ISP$M_ISR_CMD_INT	<^X10>
$EQU	ISP$M_ISR_DATA_INT	<^X20>
$EQU	ISP$M_SEMAPHORE_LOCK	<^X1>
$EQU	ISP$M_SEMAPHORE_STATUS	<^X2>
$EQU	ISP$K_NVRAM_WRITE_ENABLE	304
$EQU	ISP$K_NVRAM_WRITE_DISABLE	256
$EQU	ISP$K_NVRAM_WRITE	320
$EQU	ISP$K_NVRAM_READ	384
$EQU	ISP$K_NVRAM_ERASE	448
$EQU	ISP$M_NVRAM_CLOCK	<^X1>
$EQU	ISP$M_NVRAM_SELECT	<^X2>
$EQU	ISP$M_NVRAM_DATA_OUT	<^X4>
$EQU	ISP$M_NVRAM_DATA_IN	<^X8>
$EQU	ISP$K_MB_STS_ALIVE	0
$EQU	ISP$K_MB_STS_CHECKSUM_ERROR	1
$EQU	ISP$K_MB_STS_SHADOW_LOAD_ERROR	2
$EQU	ISP$K_MB_STS_BUSY	4
;  Command complete status codes returned in Outgoing Mailbox 0
$EQU	ISP$K_MB_STS_COMMAND_COMPLETE	16384
$EQU	ISP$K_MB_STS_INVALID_COMMAND	16385
$EQU	ISP$K_MB_STS_HOST_INTFC_ERROR	16386
$EQU	ISP$K_MB_STS_TEST_FAILED	16387
$EQU	ISP$K_MB_STS_COMMAND_ERROR	16389
$EQU	ISP$K_MB_STS_PARAMETER_ERROR	16390
;  Asynchronous event status codes returned in Outgoing Mailbox 0
$EQU	ISP$K_MB_STS_SCSI_BUS_RESET	32769
$EQU	ISP$K_MB_STS_SYSTEM_ERROR	32770
$EQU	ISP$K_MB_STS_REQUEST_XFER_ERROR	32771
$EQU	ISP$K_MB_STS_RESPONSE_XFER_ERROR	32772
$EQU	ISP$K_MB_STS_REQUEST_Q_WAKEUP	32773
$EQU	ISP$K_MB_STS_TIMEOUT_RESET	32774
$EQU	ISP$K_MB_STS_OVERRUN_NO_RESET	32780
$EQU	ISP$K_MB_STS_OVERRUN_WITH_RESET	32781
;  Commands loaded into Incoming Mailbox 0
$EQU	ISP$K_MB_NOP	0
$EQU	ISP$K_MB_LOAD_RAM	1
$EQU	ISP$K_MB_EXEC_FIRMWARE	2
$EQU	ISP$K_MB_DUMP_RAM	3
$EQU	ISP$K_MB_WRITE_RAM_WORD	4
$EQU	ISP$K_MB_READ_RAM_WORD	5
$EQU	ISP$K_MB_REGISTER_TEST	6
$EQU	ISP$K_MB_VERIFY_CHECKSUM	7
$EQU	ISP$K_MB_ABOUT_FIRMWARE	8
$EQU	ISP$K_MB_CHECKSUM_FIRMWARE	14
$EQU	ISP$K_MB_INIT_REQUEST_Q	16
$EQU	ISP$K_MB_INIT_RESPONSE_Q	17
$EQU	ISP$K_MB_EXEC_IOCB	18
$EQU	ISP$K_MB_WAKEUP	19
$EQU	ISP$K_MB_STOP_FIRMWARE	20
$EQU	ISP$K_MB_ABORT	21
$EQU	ISP$K_MB_ABORT_DEVICE	22
$EQU	ISP$K_MB_ABORT_TARGET	23
$EQU	ISP$K_MB_BUS_RESET	24
$EQU	ISP$K_MB_STOP_Q	25
$EQU	ISP$K_MB_START_Q	26
$EQU	ISP$K_MB_SINGLE_STEP_Q	27
$EQU	ISP$K_MB_ABORT_Q	28
$EQU	ISP$K_MB_GET_DEVICE_Q_STATUS	29
$EQU	ISP$K_MB_GET_FIRMWARE_STATUS	31
$EQU	ISP$K_MB_GET_INITIATOR_SCSI_ID	32
$EQU	ISP$K_MB_GET_SELECTION_TIMEOUT	33
$EQU	ISP$K_MB_GET_RETRY_COUNT	34
$EQU	ISP$K_MB_GET_TAG_AGE_LIMIT	35
$EQU	ISP$K_MB_GET_CLOCK_RATE	36
$EQU	ISP$K_MB_GET_ACTIVE_NEGATION	37
$EQU	ISP$K_MB_GET_ASYNCH_SETUP_TIME	38
$EQU	ISP$K_MB_GET_PCI_CONTROL_PARAMS	39
$EQU	ISP$K_MB_GET_TARGET_PARAMS	40
$EQU	ISP$K_MB_GET_DEVICE_Q_PARAMS	41
$EQU	ISP$K_MB_SET_INITIATOR_SCSI_ID	48
$EQU	ISP$K_MB_SET_SELECTION_TIMEOUT	49
$EQU	ISP$K_MB_SET_RETRY_COUNT	50
$EQU	ISP$K_MB_SET_TAG_AGE_LIMIT	51
$EQU	ISP$K_MB_SET_CLOCK_RATE	52
$EQU	ISP$K_MB_SET_ACTIVE_NEGATION	53
$EQU	ISP$K_MB_SET_ASYNCH_SETUP_TIME	54
$EQU	ISP$K_MB_SET_PCI_CONTROL_PARAMS	55
$EQU	ISP$K_MB_SET_TARGET_PARAMETERS	56
$EQU	ISP$K_MB_RETURN_BIOS_BLOCK_ADDRESS	64
$EQU	ISP$K_MB_WRITE_FOUR_RAM_WORDS	65
$EQU	ISP$K_MB_EXECUTE_BIOS_IOCB	66
$EQU	ISP$K_MB_SET_OVERRUN_RECOVERY_MODE	90
$EQU	ISP$K_MB_GET_OVERRUN_RECOVERY_MODE	91
; 
$EQU	ISP$K_MB_ENABLE_TARGET	85
$EQU	ISP$K_MB1_ENABLE_TARGET	32768
$EQU	ISP$K_MB1_DISABLE_TARGET	0
$EQU	ISP$K_MB_GET_TARGET_STATUS	86
; 
$EQU	ISP$K_MB_LOAD_RAM_A64	80
$EQU	ISP$K_MB_DUMP_RAM_A64	81
$EQU	ISP$K_MB_INIT_REQUESTQ_A64	82
$EQU	ISP$K_MB_INIT_RESPONSEQ_A64	82
$EQU	ISP$K_MB1_PAD_OVERFLOW	0
$EQU	ISP$K_MB1_INTERRUPT_WITHOUT_RESET	1
$EQU	ISP$K_MB1_INTERRUPT_WITH_RESET	2
$EQU	ISP$M_PSR_ALWAYS_FALSE	<^X1>
$EQU	ISP$M_PSR_INT_PENDING	<^X2>
$EQU	ISP$M_PSR_HOST_INT_STATUS	<^X4>
$EQU	ISP$M_PSR_SCSI_INT_STATUS	<^X8>
$EQU	ISP$M_PSR_DMA_IMT_STATUS	<^X10>
$EQU	ISP$M_PSR_60MHZ_CLOCK	<^X20>
$EQU	ISP$M_PSR_RESERVED_BIT6	<^X40>
$EQU	ISP$M_PSR_RESERVED_BIT7	<^X80>
$EQU	ISP$M_PSR_ALU_ZERO	<^X100>
$EQU	ISP$M_PSR_ALU_CARRY	<^X200>
$EQU	ISP$M_PSR_ALU_MSB	<^X400>
$EQU	ISP$M_PSR_ALU_OVERFLOW	<^X800>
$EQU	ISP$M_PSR_TIMER_ROLLOVER	<^X1000>
$EQU	ISP$M_PSR_RISC_INT	<^X2000>
$EQU	ISP$M_PSR_LOOP_COUNT_DONE	<^X4000>
$EQU	ISP$M_PSR_ALWAYS_TRUE	<^X8000>
$EQU	ISP$M_HCCR_BIOS_ENABLE	<^X1>
$EQU	ISP$M_HCCR_BPT_INT_ENABLE	<^X2>
$EQU	ISP$M_HCCR_BPT_0_ENABLE	<^X4>
$EQU	ISP$M_HCCR_BPT_1_ENABLE	<^X8>
$EQU	ISP$M_HCCR_BPT_EXT_ENABLE	<^X10>
$EQU	ISP$M_HCCR_PAUSE_MODE	<^X20>
$EQU	ISP$M_HCCR_RESET_MODE	<^X40>
$EQU	ISP$M_HCCR_HOST_INTERRUPT	<^X80>
$EQU	ISP$M_HCCR_COMMAND	<^XF000>
$EQU	ISP$K_HCCR_NOP	0               ;  Say Nahthing
$EQU	ISP$K_HCCR_RESET	4096    ;  Hard reset the RISC
$EQU	ISP$K_HCCR_PAUSE	8192    ;  Pause the RISC
$EQU	ISP$K_HCCR_RELEASE	12288   ;  Release the RISC after pause/reset
$EQU	ISP$K_HCCR_STEP	16384           ;  Single-step the RISC
$EQU	ISP$K_HCCR_SET_HOST_INT	20480   ;  Set host-to-RISC interrupt
$EQU	ISP$K_HCCR_CLR_HOST_INT	24576   ;  Clear host-to-RISC interrupt
$EQU	ISP$K_HCCR_CLR_RISC_INT	28672   ;  Clear RISC-to-host interrupt
$EQU	ISP$K_HCCR_WRITE_BPT	32768   ;  Allow write to BPT bits
$EQU	ISP$K_HCCR_WRITE_BIOS	36864   ;  Allow write to BIOS bit
$EQU	ISP$K_BI_HCCR_CMD_TEST_MODE	15 ;  Set chip test mode
$EQU	ISP$S_ISP_REGISTERS	248
;  Bus interface registers
$EQU	ISP$W_BUS_ID_LOW	0       ;  Unique ID low word (Vendor code)
$EQU	ISP$W_BUS_ID_HIGH	2       ;  Unique ID high word (Product code)
$EQU	ISP$W_BUS_CONFIG_0	4       ;  Hardware Revision <3:0>
$EQU	ISP$W_BUS_CONFIG_1	6       ; 
$EQU	ISP$S_CONFIG_1_FIFO_THRESH	2
$EQU	ISP$V_CONFIG_1_FIFO_THRESH	0 ;  Threshhold at which PCI bursts are
;   requested
$EQU	ISP$V_CONFIG_1_BURST_ENABLE	2 ;  Enable burst mode
$EQU	ISP$V_CONFIG_1_SEL_SXP_REGS	3 ;  Select SXP register set
$EQU	ISP$W_BUS_ICR	8               ;  Interface Control Register
$EQU	ISP$V_ICR_SOFT_RESET	0       ;  Reset the ISP after cur cycle
$EQU	ISP$V_ICR_ALL_INT_ENB	1       ;  Enables/disables all of the following:
$EQU	ISP$V_ICR_RISC_INT_ENB	2       ;   RISC processor interrupt enable
$EQU	ISP$V_ICR_SXP_INT_ENB	3       ;   SCSI processor interrupt enable
$EQU	ISP$V_ICR_CMD_INT_ENB	4       ;   DMA command channel interrupt enable
$EQU	ISP$V_ICR_DATA_INT_ENB	5       ;   DMA data channel interrupt enable
$EQU	ISP$W_BUS_ISR	10              ;  Interface Status Register
$EQU	ISP$V_ISR_ALL_INT	1       ;  Interrupt request from the following:
$EQU	ISP$V_ISR_RISC_INT	2       ;   RISC processor interrupt request
$EQU	ISP$V_ISR_SXP_INT	3       ;   SCSI processor interrupt request
$EQU	ISP$V_ISR_CMD_INT	4       ;   DMA command channel interrupt request
$EQU	ISP$V_ISR_DATA_INT	5       ;   DMA data channel interrupt request
$EQU	ISP$W_BUS_SEMAPHORE	12      ;  Semaphore register
$EQU	ISP$V_SEMAPHORE_LOCK	0       ;  Semaphore lock request
$EQU	ISP$V_SEMAPHORE_STATUS	1       ;  Semaphore lock status
$EQU	ISP$W_BUS_NVRAM	14              ;  NVRAM Interface Register
$EQU	ISP$V_NVRAM_CLOCK	0       ;  Clock for NVRAM data shift
$EQU	ISP$V_NVRAM_SELECT	1       ;  Select the NVRAM chip for R/W 
$EQU	ISP$V_NVRAM_DATA_OUT	2       ;  Write data to NVRAM
$EQU	ISP$V_NVRAM_DATA_IN	3       ;  Read data from NVRAM
$EQU	ISP$W_DMA_CMD_CONFIG	32      ;  DMA command config register
$EQU	ISP$W_DMA_CMD_CONTROL	34      ;  DMA command control register
$EQU	ISP$W_DMA_CMD_STATUS	36      ;  DMA command status register
$EQU	ISP$W_DMA_CMD_FIFO	38      ;  DMA command FIFO status register
$EQU	ISP$W_DMA_CMD_XFR_LOW	40      ;  DMA command transfer count register
$EQU	ISP$W_DMA_CMD_ADDR_LOW	44      ;  DMA command address low register
$EQU	ISP$W_DMA_CMD_ADDR_HIGH	46      ;  DMA command address high register
$EQU	ISP$W_DMA_DATA_CONFIG	64      ;  DMA data config register
$EQU	ISP$W_DMA_DATA_CONTROL	66      ;  DMA data control register
$EQU	ISP$W_DMA_DATA_STATUS	68      ;  DMA data status register
$EQU	ISP$W_DMA_DATA_FIFO	70      ;  DMA fifo status register
$EQU	ISP$W_DMA_DATA_XFR_LOW	72      ;  DMA data transfer count low register
$EQU	ISP$W_DMA_DATA_XFR_HIGH	74      ;  DMA data transfer count high register
$EQU	ISP$W_DMA_DATA_ADDR_LOW	76      ;  DMA data transfer address low register
$EQU	ISP$W_DMA_DATA_ADDR_HIGH	78 ;  DMA data transfer address high register
$EQU	ISP$W_DMA_CMD_FIFO_PORT	96      ;  DMA command FIFO_PORT register
$EQU	ISP$W_DMA_DATA_FIFO_PORT	98 ;  DMA data FIFO_PORT register
$EQU	ISP$W_MAILBOX_0	112             ;  Mailbox register 0
;  Self-test status codes returned in Outgoing Mailbox 0
; 	Target mode codes
;  
; 	64 bit extensions
; 		    
$EQU	ISP$W_MAILBOX_1	114             ;  Mailbox register 1
;    These constants are the mailbox 1 values for the set overrun recovery    
;    mode command  							      
$EQU	ISP$W_MAILBOX_2	116             ;  Mailbox register 2
$EQU	ISP$W_MAILBOX_3	118             ;  Mailbox register 3
$EQU	ISP$W_MAILBOX_4	120             ;  Mailbox register 4
$EQU	ISP$W_MAILBOX_5	122             ;  Mailbox register 5
$EQU	ISP$S_RISC_REGS	74
$EQU	ISP$R_RISC_REGS	128
$EQU	ISP$W_RISC_ACC	128             ;  RISC accumulator
$EQU	ISP$W_RISC_R1	130             ;  GPR 1
$EQU	ISP$W_RISC_R2	132             ;  GPR 2
$EQU	ISP$W_RISC_R3	134             ;  GPR 3
$EQU	ISP$W_RISC_R4	136             ;  GPR 4
$EQU	ISP$W_RISC_R5	138             ;  GPR 5
$EQU	ISP$W_RISC_R6	140             ;  GPR 6
$EQU	ISP$W_RISC_R7	142             ;  GPR 7
$EQU	ISP$W_RISC_R8	144             ;  GPR 8
$EQU	ISP$W_RISC_R9	146             ;  GPR 9
$EQU	ISP$W_RISC_R10	148             ;  GPR 10
$EQU	ISP$W_RISC_R11	150             ;  GPR 11
$EQU	ISP$W_RISC_R12	152             ;  GPR 12
$EQU	ISP$W_RISC_R13	154             ;  GPR 13
$EQU	ISP$W_RISC_R14	156             ;  GPR 14
$EQU	ISP$W_RISC_R15	158             ;  GPR 15
$EQU	ISP$W_RISC_PSR	160             ;  RISC processor status register
$EQU	ISP$V_PSR_ALWAYS_FALSE	0
$EQU	ISP$V_PSR_INT_PENDING	1
$EQU	ISP$V_PSR_HOST_INT_STATUS	2
$EQU	ISP$V_PSR_SCSI_INT_STATUS	3
$EQU	ISP$V_PSR_DMA_IMT_STATUS	4
$EQU	ISP$V_PSR_60MHZ_CLOCK	5
$EQU	ISP$V_PSR_RESERVED_BIT6	6
$EQU	ISP$V_PSR_RESERVED_BIT7	7
$EQU	ISP$V_PSR_ALU_ZERO	8
$EQU	ISP$V_PSR_ALU_CARRY	9
$EQU	ISP$V_PSR_ALU_MSB	10
$EQU	ISP$V_PSR_ALU_OVERFLOW	11
$EQU	ISP$V_PSR_TIMER_ROLLOVER	12
$EQU	ISP$V_PSR_RISC_INT	13
$EQU	ISP$V_PSR_LOOP_COUNT_DONE	14
$EQU	ISP$V_PSR_ALWAYS_TRUE	15
$EQU	ISP$W_RISC_IVR	162             ;  RISC interrupt vector register
$EQU	ISP$W_RISC_PCR	164             ;  RISC processor control register
$EQU	ISP$W_RISC_RAR0	166             ;  RISC address register 0
$EQU	ISP$W_RISC_RAR1	168             ;  RISC address register 1
$EQU	ISP$W_RISC_LCR	170             ;  RISC loop count register
$EQU	ISP$W_RISC_PC	172             ;  RISC program counter
$EQU	ISP$W_RISC_MTR_OVERLAY	174     ;  RISC memory timing register
$EQU	ISP$W_RISC_EMB	176             ;  RISC external memory boundary
$EQU	ISP$W_RISC_SP	178             ;  RISC stack pointer
$EQU	ISP$W_RISC_HARDWARE_REV	180     ;  RISC hardware revision register
$EQU	ISP$W_HCCR	192             ;  Host Command and Control Register
$EQU	ISP$V_HCCR_BIOS_ENABLE	0       ;  Enable BIOS accesses
$EQU	ISP$V_HCCR_BPT_INT_ENABLE	1 ;  Enable interrupt on RISC breakpoint
$EQU	ISP$V_HCCR_BPT_0_ENABLE	2       ;  Enable breakpoint 0
$EQU	ISP$V_HCCR_BPT_1_ENABLE	3       ;  Enable breakpoint 1
$EQU	ISP$V_HCCR_BPT_EXT_ENABLE	4 ;  Enable external breakpoint
$EQU	ISP$V_HCCR_PAUSE_MODE	5       ;  RISC processor is paused
$EQU	ISP$V_HCCR_RESET_MODE	6       ;  RISC processor is reset
$EQU	ISP$V_HCCR_HOST_INTERRUPT	7 ;  Host interrupt is active
$EQU	ISP$S_HCCR_COMMAND	4
$EQU	ISP$V_HCCR_COMMAND	12      ;  HCCR command
$EQU	ISP$W_PB0	194             ;  Processor breakpoint 0 register
$EQU	ISP$W_PB1	196             ;  Processor breakpoint 1 register
$EQU	ISP$W_TCR	198             ;  Test control register
$EQU	ISP$W_TMR	200             ;  Test mode register
$EQU	ISP$S_SXP_REGS	120
$EQU	ISP$R_SXP_REGS	128
$EQU	ISP$W_SXP_PART_ID	128     ;  Part ID code
$EQU	ISP$W_SXP_CONFIG_1	130     ;  Configuration register 1
$EQU	ISP$W_SXP_CONFIG_2	132     ;  Configuration register 2
$EQU	ISP$W_SXP_CONFIG_3	134     ;  Configuration register 3
$EQU	ISP$W_SXP_INST_PTR	140     ;  Instruction pointer
$EQU	ISP$W_SXP_RET_ADDR	144     ;  Return address
$EQU	ISP$W_SXP_COMMAND	148     ;  Command register
$EQU	ISP$W_SXP_INTERRUPT	152     ;  Interrupt register
$EQU	ISP$W_SXP_SEQUENCE	156     ;  Sequence register
$EQU	ISP$W_SXP_GROSS_ERR	158     ;  Gross error register
$EQU	ISP$W_SXP_EXCEPT_ENB	160     ;  Exception enable register
$EQU	ISP$W_SXP_OVERRIDE	164     ;  Override register
$EQU	ISP$W_SXP_LIT_BASE	168     ;  Literal base register
$EQU	ISP$W_SXP_USER_FLAGS	172     ;  User flags register
$EQU	ISP$W_SXP_USER_EXCEPT	176     ;  User exception register
$EQU	ISP$W_SXP_BPT	180             ;  Breakpoint register
$EQU	ISP$W_SXP_SCSI_ID	192     ;  SCSI ID register
$EQU	ISP$W_SXP_DEV_CFG_1	194     ;  SCSI device configuration 1
$EQU	ISP$W_SXP_DEV_CFG_2	196     ;  SCSI device configuration 2
$EQU	ISP$W_SXP_PHASE_PTR	200     ;  SCSI phase pointer register
$EQU	ISP$W_SXP_BFR_POINTER	204     ;  SCSI buffer pointer register
$EQU	ISP$W_SXP_BFR_COUNTER	208     ;  SCSI buffer counter register
$EQU	ISP$W_SXP_BUFFER	210     ;  SCSI buffer register
$EQU	ISP$W_SXP_BFR_BYTE	212     ;  SCSI buffer byte register
$EQU	ISP$W_SXP_BFR_WORD	214     ;  SCSI buffer word register
$EQU	ISP$W_SXP_BFR_WORD_XLT	216     ;  SCSI buffer word translate register
$EQU	ISP$W_SXP_FIFO	218             ;  SCSI FIFO
$EQU	ISP$W_SXP_FIFO_STATUS	220     ;  SCSI FIFO status register
$EQU	ISP$W_SXP_FIFO_TOP_RESID	222 ;  SCSI FIFO top residue
$EQU	ISP$W_SXP_FIFO_BOT_RESID	224 ;  SCSI FIFO bottom residue
$EQU	ISP$W_SXP_XFR	228             ;  SCSI transfer register
$EQU	ISP$W_SXP_XFR_COUNT_LOW	232     ;  SCSI transfer count low
$EQU	ISP$W_SXP_XFR_COUNT_HIGH	234 ;  SCSI transfer count high
$EQU	ISP$W_SXP_XFR_CTR_LOW	236     ;  SCSI transfer counter low
$EQU	ISP$W_SXP_XFR_CTR_HIGH	238     ;  SCSI transfer counter high
$EQU	ISP$W_SXP_ARBIT	240             ;  SCSI arbitration data
$EQU	ISP$W_SXP_CNTRL_PINS	242     ;  SCSI control pins
$EQU	ISP$W_SXP_DATA_PINS	244     ;  SCSI data pins
$EQU	ISP$W_SXP_DIFF_PINS	246     ;  SCSI differential control pins
$EQU	ISP$K_REG_FILE_SIZE	248     ;  Length of register file
$EQU	ISP$K_SXP_REG_SIZE	120     ;  Length of SXP register file
$EQU	ISP$K_NVR_MIN_VERSION	2       ;  Minimum acceptable version
$EQU	ISP$K_NVR_FIFO_THRESHHOLD	2 ;   defaults to 32 bytes
$EQU	ISP$K_NVR_ADAPTOR_ENABLE	1 ;   defaults to enabled (1)
$EQU	ISP$K_NVR_INITIATOR_SCSI_ID	7 ;   defaults to 7
$EQU	ISP$K_NVR_BUS_RESET_DELAY	1 ;   defaults to 1 second
$EQU	ISP$K_NVR_RETRY_COUNT	0       ;   defaults to 0 retries
$EQU	ISP$K_NVR_RETRY_DELAY	1       ;   defaults to 1 second
$EQU	ISP$K_NVR_ASYNCH_SETUP_TIME	6 ;   defaults to 6 clock periods
$EQU	ISP$K_NVR_REQ_ACK_ACTIVE_NEGATION	1 ;   defaults to enabled (1)
$EQU	ISP$K_NVR_DATA_ACTIVE_NEGATION	1 ;   defaults to enabled (1)
$EQU	ISP$K_NVR_DATA_DMA_BURST_ENABLE	1 ;   defaults to enabled (1)
$EQU	ISP$K_NVR_COMMAND_DMA_BURST_ENABLE	1 ;   defaults to enabled (1)
$EQU	ISP$K_NVR_TAG_AGE_LIMIT	8       ;   defaults to a tag count of 8
$EQU	ISP$K_NVR_TERMINATION_LOW_ENABLE	1 ;   defaults to enabled (1)
$EQU	ISP$K_NVR_TERMINATION_HIGH_ENABLE	1 ;   defaults to enabled (1)
$EQU	ISP$K_NVR_PCMC_BURST_ENABLE	0 ;   defaults to disabled (0)
$EQU	ISP$K_NVR_60MHZ_ENABLE	0       ;   defaults to disabled (0)
$EQU	ISP$K_NVR_SELECTION_TIMEOUT	250 ;   defaults to 250ms
$EQU	ISP$K_NVR_MAX_QUEUE_DEPTH	256 ;   defaults to 256 entries
$EQU	ISP$M_NVR_RENEGOTIATE_ON_ERROR	<^X1>
$EQU	ISP$K_NVR_RENEGOTIATE_ON_ERROR	1 ;   defaults to enabled (1)
$EQU	ISP$M_NVR_STOP_QUEUE_ON_CHECK	<^X2>
$EQU	ISP$K_NVR_STOP_QUEUE_ON_CHECK	0 ;   defaults to disabled (0)
$EQU	ISP$M_NVR_AUTO_REQUEST_SENSE	<^X4>
$EQU	ISP$K_NVR_AUTO_REQUEST_SENSE	1 ;   defaults to enabled (1)
$EQU	ISP$M_NVR_TAGGED_QUEUING	<^X8>
$EQU	ISP$K_NVR_TAGGED_QUEUING	1 ;   defaults to enabled (1)
$EQU	ISP$M_NVR_SYNCH_DATA_TRANSFERS	<^X10>
$EQU	ISP$K_NVR_SYNCH_DATA_TRANSFERS	1 ;   defaults to enabled (1)
$EQU	ISP$M_NVR_WIDE_DATA_TRANSFERS	<^X20>
$EQU	ISP$K_NVR_WIDE_DATA_TRANSFERS	1 ;   defaults to enabled (1)
$EQU	ISP$M_NVR_PARITY_CHECKING	<^X40>
$EQU	ISP$K_NVR_PARITY_CHECKING	1 ;   defaults to enabled (1)
$EQU	ISP$M_NVR_DISCONNECT_ALLOWED	<^X80>
$EQU	ISP$K_NVR_DISCONNECT_ALLOWED	1 ;   defaults to enabled (1)
$EQU	ISP$K_NVR_EXECUTION_THROTTLE	16 ;   defaults to 16 requests per device
$EQU	ISP$K_NVR_SYNCH_PERIOD	25      ;   defaults to 25 (100ns)
$EQU	ISP$K_NVR_SYNCH_OFFSET	12      ;   defaults to 12 unACK'ed REQs
$EQU	ISP$K_NVR_DEVICE_ENABLE	1       ;   defaults to enabled (1)
$EQU	ISP$S_ISP_NVRAM	128
;  NVRAM adaptor-wide parameters
$EQU	ISP$S_NVR_ID	4
$EQU	ISP$B_NVR_ID	0               ;  NVRAM signature: "ISP "
$EQU	ISP$B_NVR_VERSION	4       ;  NVRAM version
$EQU	ISP$S_NVR_FIFO_THRESHHOLD	2
$EQU	ISP$V_NVR_FIFO_THRESHHOLD	40 ;  FIFO threshhold see BUS_CONFIG1 register
$EQU	ISP$V_NVR_RESERVED_0	42
$EQU	ISP$V_NVR_ADAPTOR_ENABLE	43 ;  Adaptor enabled
$EQU	ISP$S_NVR_INITIATOR_SCSI_ID	4
$EQU	ISP$V_NVR_INITIATOR_SCSI_ID	44 ;  Initiator SCSI ID
$EQU	ISP$B_NVR_BUS_RESET_DELAY	6 ;  Delay after reset until 1st command issued
$EQU	ISP$B_NVR_RETRY_COUNT	7       ;  Error retry count
$EQU	ISP$B_NVR_RETRY_DELAY	8       ;  Delay between error retries
$EQU	ISP$S_NVR_ASYNCH_SETUP_TIME	4
$EQU	ISP$V_NVR_ASYNCH_SETUP_TIME	72 ;  Asynchronous setup time (clock periods)
$EQU	ISP$V_NVR_REQ_ACK_ACTIVE_NEGATION	76 ;  Enable SCSI REQ/ACK active pullups
$EQU	ISP$V_NVR_DATA_ACTIVE_NEGATION	77 ;  Enable SCSI Data active pullups
$EQU	ISP$V_NVR_DATA_DMA_BURST_ENABLE	78 ;  Data DMA channel burst enable
$EQU	ISP$V_NVR_COMMAND_DMA_BURST_ENABLE	79 ;  Command DMA channel burst enable
$EQU	ISP$B_NVR_TAG_AGE_LIMIT	10      ;  Tag aging limit counter
$EQU	ISP$V_NVR_TERMINATION_LOW_ENABLE	88 ;  Enable termination of low 8 bits
$EQU	ISP$V_NVR_TERMINATION_HIGH_ENABLE	89 ;  Enable termination of high 8 bits
$EQU	ISP$V_NVR_PCMC_BURST_ENABLE	90 ;  PCMC burst enable
$EQU	ISP$V_NVR_60MHZ_ENABLE	91      ;  Enable 60MHZ ISP1020 clock
$EQU	ISP$S_NVR_RESERVED_1	4
$EQU	ISP$V_NVR_RESERVED_1	92
$EQU	ISP$W_NVR_SELECTION_TIMEOUT	12 ;  Selection timeout (ms)
$EQU	ISP$W_NVR_MAX_QUEUE_DEPTH	14 ;  Maximum queue depth
;  Per-target parameters
$EQU	ISP$S_NVR_TARGET	96
$EQU	ISP$R_NVR_TARGET	28
$EQU	ISP$B_NVR_CAPABILITES	28
$EQU	ISP$V_NVR_RENEGOTIATE_ON_ERROR	0 ;  Renegotiate wide/synch on check condition
$EQU	ISP$V_NVR_STOP_QUEUE_ON_CHECK	1 ;  Stop queue on check if auto req sense set
$EQU	ISP$V_NVR_AUTO_REQUEST_SENSE	2 ;  Do auto request sense on check condition
$EQU	ISP$V_NVR_TAGGED_QUEUING	3 ;  Tagged queuing support
$EQU	ISP$V_NVR_SYNCH_DATA_TRANSFERS	4 ;  Synchronous data transfers
$EQU	ISP$V_NVR_WIDE_DATA_TRANSFERS	5 ;  Wide data transfers enabled
$EQU	ISP$V_NVR_PARITY_CHECKING	6 ;  Parity checking enabled
$EQU	ISP$V_NVR_DISCONNECT_ALLOWED	7 ;  Disconnect privilege enabled
$EQU	ISP$B_NVR_EXECUTION_THROTTLE	29 ;  Maximum commands issued to device
$EQU	ISP$B_NVR_SYNCH_PERIOD	30      ;  Synchronous transfer period (4ns units)
$EQU	ISP$S_NVR_SYNCH_OFFSET	4
$EQU	ISP$V_NVR_SYNCH_OFFSET	24      ;  REQ/ACK offset
$EQU	ISP$V_NVR_DEVICE_ENABLE	28      ;  Device enabled
$EQU	ISP$B_NVR_CHECKSUM	127     ;  NVRAM additive checksum
$EQU	ISP$K_NVRAM_SIZE	128
	$DEFEND	ISP1020,$GBL,DEF
	.ENDM