! ********************************************************************************************************************************
*2D
 !  Created  8-NOV-1988 16:06:49 by VAX SDL T3.2-9      Source:  8-JAN-1988 11:39:53 SRC_1:[VMS050.DRIVER.LIS]PEM_DEF.SDL;1 
*2E
*2I
*3D
 !  Created 15-SEP-1988 22:22:21 by VAX-11 SDL V3.1-7      Source: 29-AUG-1988 09:05:11 _$254$DUA224:[DRIVER.SRC]PEM_DEF.SDL;1 
*3E
*3I
*4D
 !  Created  8-NOV-1988 16:06:49 by VAX SDL T3.2-9      Source:  8-JAN-1988 11:39:53 SRC_1:[VMS050.DRIVER.LIS]PEM_DEF.SDL;1 
*4E
*4I
*5D
 !  Created 15-SEP-1988 22:22:21 by VAX-11 SDL V3.1-7      Source: 29-AUG-1988 09:05:11 _$254$DUA224:[DRIVER.SRC]PEM_DEF.SDL;1 
*5E
*5I
 !  Created 12-OCT-1989 22:03:36 by VAX SDL T3.2-8      Source:  4-OCT-1989 11:01:58 _$11$DUA26:[DRIVER.SRC]PEM_DEF.SDL;2 
*5E
*4E
*3E
*2E
 ! ********************************************************************************************************************************
  
*2D
 !*** MODULE $NISCADEF ***
*2E
*2I
*3D
 !*** MODULE NISCA ***
*3E
*3I
*4D
 !*** MODULE $NISCADEF ***
*4E
*4I
 !*** MODULE NISCA ***
*4E
*3E
*2E
 literal NISCA$C_DX_LNG_HDR = 14;
 literal NISCA$C_HELLO = 0;
 literal NISCA$C_BYE = 1;
 literal NISCA$C_CCSTART = 2;
 literal NISCA$C_VERF = 3;
 literal NISCA$C_VACK = 4;
 literal NISCA$C_DONE = 5;
*5I
 literal NISCA$C_SOLICIT_SRV = 6;
*5E
 literal NISCA$m_spx = 15;
 literal NISCA$M_AUTHORIZE = 16;
 literal NISCA$M_OK_XMT = 32;
 literal NISCA$M_NO_XMT = 64;
 literal NISCA$M_CCFLG = 128;
 literal NISCA$M_MAINT_ID = 2147483647;
 literal NISCA$M_D = -2147483648;
 literal NISCA$M_MAINT = -2147483640;
 literal NISCA$M_PORT_FCN = -2080440064;
 literal NISCA$M_M = 256;
 literal NISCA$M_PS = 1536;
 literal NISCA$M_SYS_STATE = -2048;
 literal NISCA$M_STA_INFO = 1024;
 literal NISCA$C_CC_LNG = 46;
*5I
 literal NISCA$C_CC_LNG_V12 = 62;
*5E
 literal NISCA$M_SRV_XCHK = 1;
 literal NISCA$M_SRV_RCHK = 2;
 literal NISCA$M_TR_DATA = 1;
 literal NISCA$M_TR_SEQ = 2;
 literal NISCA$M_TR_NAK = 4;
 literal NISCA$M_TR_ACK = 8;
 literal NISCA$M_TR_RSVP = 16;
 literal NISCA$M_TR_MBZ = 32;
 literal NISCA$M_TR_CTL = 64;
 literal NISCA$M_TR_CCFLG = 128;
 literal NISCA$C_TR_LNG_HDR = 6;
 literal NISCA$C_GROUP_BASE_LO = 17039531;
 literal NISCA$C_GROUP_BASE_HI = 256;
 literal NISCA$C_GROUP_MAX = 65279;
 literal NISCA$C_NI_PROTOCOL = 1888;
 literal NISCA$C_NI_ACCESS_CODE = 6007;
 literal NISCA$C_DELAY_ACK = 1;
 literal NISCA$C_DELAY_SEQ = 2;
 literal NISCA$C_TIMER = 10000000;
 literal NISCA$C_HS_TIMER = 5;
 literal NISCA$C_HELLO_TIMER = 3;
 literal NISCA$C_DELAY_XSPRT = 1;
 literal NISCA$C_PIPE_QUOTA = 8;
 literal NISCA$C_MAX_CACHE = 8;
 literal NISCA$C_MAX_REXMT = 30;
*5D
 literal NISCA$C_MINOR = 1;
*5E
 literal NISCA$C_MAJOR = 1;
*5I
 literal NISCA$C_MINOR = 2;
*5E
 literal NISCA$C_ECO = 0;
 literal NISCA$C_MAX_VCTMO = 16;
*2I
*3D
 literal NISCA$C_CMDQ_3 = 0;
 literal NISCA$C_CMDQ_2 = 1;
 literal NISCA$C_CMDQ_HI = 2;
 literal NISCA$C_CMDQ_LO = 3;
*3E
*2E
*4I
 literal NISCA$C_CMDQ_3 = 0;
 literal NISCA$C_CMDQ_2 = 1;
 literal NISCA$C_CMDQ_HI = 2;
 literal NISCA$C_CMDQ_LO = 3;
*4E
 literal NISCA$C_SNT_DG = 0;
 literal NISCA$C_SNT_LB = 1;
 literal NISCA$C_SNT_SEQ = 2;
 literal NISCA$C_SNT_DATM = 3;
 literal NISCA$C_SNT_DAT = 4;
 literal NISCA$C_SNT_DAT_LP = 5;
 literal NISCA$C_REQ_ID = 6;
 literal NISCA$C_REQ_DATM = 7;
 literal NISCA$C_REQ_DAT0 = 8;
 literal NISCA$C_REQ_DAT1 = 9;
 literal NISCA$C_REQ_DAT2 = 10;
 literal NISCA$C_RET_DATM = 11;
 literal NISCA$C_RET_DAT = 12;
 literal NISCA$C_RET_DAT_LP = 13;
 literal NISCA$C_RET_CNFM = 14;
 literal NISCA$C_RET_CNF = 15;
 literal NISCA$C_RET_ID = 16;
 literal NISCA$C_RET_LB = 17;
 literal NISCA$C_RESET = 18;
 literal NISCA$C_START = 19;
 literal NISCA$C_PPDMSG_MAX = 19;
 literal NISCA$C_SIZ_BLKDAT = 1024;
*5D
 literal NISCA$S_NISCADEF = 46;
*5E
*5I
 literal NISCA$S_NISCADEF = 62;
*5E
 macro NISCA$L_DX_DST_LO = 0,0,32,0 %;
 macro NISCA$W_DX_DST_HI = 4,0,16,0 %;
 macro NISCA$W_DX_GROUP = 6,0,16,0 %;
 macro NISCA$L_DX_SRC_LO = 8,0,32,0 %;
 macro NISCA$W_DX_SRC_HI = 12,0,16,0 %;
 macro NISCA$B_MSG = 0,0,8,0 %;
 macro NISCA$V_AUTHORIZE = 0,4,1,0 %;
 macro NISCA$V_OK_XMT = 0,5,1,0 %;
 macro NISCA$V_NO_XMT = 0,6,1,0 %;
 macro NISCA$V_CCFLG = 0,7,1,0 %;
 macro NISCA$B_REASON = 1,0,8,0 %;
 macro NISCA$L_MAINT = 2,0,32,0 %;
 macro NISCA$V_MAINT_ID = 2,0,31,0 %;
 literal NISCA$S_MAINT_ID = 31;
 macro NISCA$V_D = 2,31,1,0 %;
 macro NISCA$B_MINOR = 6,0,8,0 %;
 macro NISCA$B_MAJOR = 7,0,8,0 %;
 macro NISCA$W_ECO = 8,0,16,0 %;
 macro NISCA$T_NODENAME = 10,0,0,0 %;
 literal NISCA$S_NODENAME = 8;
 macro NISCA$L_PORT_FCN = 18,0,32,0 %;
 macro NISCA$L_STA_INFO = 22,0,32,0 %;
 macro NISCA$V_M = 22,8,1,0 %;
 macro NISCA$V_PS = 22,9,2,0 %;
 literal NISCA$S_PS = 2;
 macro NISCA$V_SYS_STATE = 22,11,21,0 %;
 literal NISCA$S_SYS_STATE = 21;
 macro NISCA$T_RST_PORT = 26,0,0,0 %;
 literal NISCA$S_RST_PORT = 6;
 macro NISCA$B_RESERVED0 = 32,0,8,0 %;
 macro NISCA$B_PIPE_QUOTA = 33,0,8,0 %;
 macro NISCA$W_P_SRV = 34,0,16,0 %;
 macro NISCA$W_R_SRV = 36,0,16,0 %;
 macro NISCA$Q_AUTHORIZE = 38,0,0,0 %;
 literal NISCA$S_AUTHORIZE = 8;
*5I
 macro NISCA$T_SERVICE = 46,0,0,0 %;
 literal NISCA$S_SERVICE = 16;
*5E
 macro NISCA$V_SRV_XCHK = 0,0,1,0 %;
 macro NISCA$V_SRV_RCHK = 0,1,1,0 %;
 macro NISCA$B_TR_FLAG = 0,0,8,0 %;
 macro NISCA$V_TR_DATA = 0,0,1,0 %;
 macro NISCA$V_TR_SEQ = 0,1,1,0 %;
 macro NISCA$V_TR_NAK = 0,2,1,0 %;
 macro NISCA$V_TR_ACK = 0,3,1,0 %;
 macro NISCA$V_TR_RSVP = 0,4,1,0 %;
 macro NISCA$V_TR_MBZ = 0,5,1,0 %;
 macro NISCA$V_TR_CTL = 0,6,1,0 %;
 macro NISCA$V_TR_CCFLG = 0,7,1,0 %;
 macro NISCA$B_TR_PAD = 1,0,8,0 %;
 macro NISCA$W_TR_ACK = 2,0,16,0 %;
 macro NISCA$W_TR_SEQ = 4,0,16,0 %;
  
*2D
 !*** MODULE $PORTQBDEF ***
*2E
*2I
*3D
 !*** MODULE PORTQB ***
*3E
*3I
*4D
 !*** MODULE $PORTQBDEF ***
*4E
*4I
 !*** MODULE PORTQB ***
*4E
*3E
*2E
 literal PORTQB$S_PORTQBDEF = 84;
*2D
 macro PORTQB$Q_CMDQ0 = 0,0,0,0 %;
 literal PORTQB$S_CMDQ0 = 8;
 macro PORTQB$Q_CMDQ1 = 8,0,0,0 %;
 literal PORTQB$S_CMDQ1 = 8;
 macro PORTQB$Q_CMDQ2 = 16,0,0,0 %;
 literal PORTQB$S_CMDQ2 = 8;
 macro PORTQB$Q_CMDQ3 = 24,0,0,0 %;
 literal PORTQB$S_CMDQ3 = 8;
*2E
*2I
*3D
 macro PORTQB$R_CMDQ_FILL = 0,0,0,0 %;
 literal PORTQB$S_CMDQ_FILL = 32;
*3E
*3I
*4D
 macro PORTQB$Q_CMDQ0 = 0,0,0,0 %;
 literal PORTQB$S_CMDQ0 = 8;
 macro PORTQB$Q_CMDQ1 = 8,0,0,0 %;
 literal PORTQB$S_CMDQ1 = 8;
 macro PORTQB$Q_CMDQ2 = 16,0,0,0 %;
 literal PORTQB$S_CMDQ2 = 8;
 macro PORTQB$Q_CMDQ3 = 24,0,0,0 %;
 literal PORTQB$S_CMDQ3 = 8;
*4E
*4I
 macro PORTQB$R_CMDQ_FILL = 0,0,0,0 %;
 literal PORTQB$S_CMDQ_FILL = 32;
*4E
*3E
*2E
 macro PORTQB$Q_RSPQ = 32,0,0,0 %;
 literal PORTQB$S_RSPQ = 8;
 macro PORTQB$L_DFQHDR = 40,0,32,0 %;
 macro PORTQB$L_MFQHDR = 44,0,32,0 %;
 macro PORTQB$W_DQELEN = 48,0,16,0 %;
 macro PORTQB$W_MQELEN = 52,0,16,0 %;
 macro PORTQB$L_VPORTQB = 56,0,32,0 %;
 macro PORTQB$L_VBDT = 60,0,32,0 %;
 macro PORTQB$W_BDTLEN = 64,0,16,0 %;
 macro PORTQB$L_SPTBASE = 68,0,32,0 %;
 macro PORTQB$L_SPTLEN = 72,0,32,0 %;
 macro PORTQB$L_GPTBASE = 76,0,32,0 %;
 macro PORTQB$L_GPTLEN = 80,0,32,0 %;
  
*2D
 !*** MODULE $BUSDEF ***
*2E
*2I
*3D
 !*** MODULE BUS ***
*3E
*3I
*4D
 !*** MODULE $BUSDEF ***
*4E
*4I
 !*** MODULE BUS ***
*4E
*3E
*2E
 literal ERR$C_LENGTH = 6;
 literal ERR$S_ERRDEF = 6;
 macro ERR$W_STATUS = 0,0,16,0 %;
 macro ERR$W_UNLOG_COUNT = 2,0,16,0 %;
 macro ERR$B_LOG_COUNT = 4,0,8,0 %;
 macro ERR$B_SP1 = 5,0,8,0 %;
 literal BUS$M_INIT = 1;
 literal BUS$M_RUN = 2;
 literal BUS$M_FATAL = 4;
 literal BUS$M_UCB = 8;
 literal BUS$M_XSPT = 16;
 literal BUS$C_NUM_COU = 6;
 literal BUS$C_NUM_RAIL = 16;
 literal BUS$C_LENGTH = 132;
 literal BUS$S_BUSDEF = 132;
 macro BUS$L_LINK = 0,0,32,0 %;
 macro BUS$L_CABLE_INX = 4,0,32,0 %;
 macro BUS$W_SIZE = 8,0,16,0 %;
 macro BUS$B_TYPE = 10,0,8,0 %;
 macro BUS$B_STS = 11,0,8,0 %;
 macro BUS$V_INIT = 11,0,1,0 %;
 macro BUS$V_RUN = 11,1,1,0 %;
 macro BUS$V_FATAL = 11,2,1,0 %;
 macro BUS$V_UCB = 11,3,1,0 %;
 macro BUS$V_XSPT = 11,4,1,0 %;
 macro BUS$L_NI_ERRCNT = 12,0,32,0 %;
 macro BUS$L_NI_LASTERR = 16,0,32,0 %;
 macro BUS$Q_NI_SYSTIME = 20,0,0,0 %;
 literal BUS$S_NI_SYSTIME = 8;
 macro BUS$AL_VEC0_ERR = 28,0,0,0 %;
 literal BUS$S_VEC0_ERR = 36;
 macro BUS$W_IOC = 64,0,16,0 %;
 macro BUS$B_CNT_RAIL = 66,0,8,0 %;
 macro BUS$B_XSPT = 67,0,8,0 %;
 macro BUS$AL_VEC0_RAIL = 68,0,0,0 %;
 literal BUS$S_VEC0_RAIL = 64;
 macro BUS$T_FFI = 132,0,0,0 %;
  
*2D
 !*** MODULE $VCDEF ***
*2E
*2I
*3D
 !*** MODULE VC ***
*3E
*3I
*4D
 !*** MODULE $VCDEF ***
*4E
*4I
 !*** MODULE VC ***
*4E
*3E
*2E
 literal RCH$C_LENGTH = 8;
 literal RCH$S_RCHDEF = 8;
 macro RCH$L_REMNI_LO = 0,0,32,0 %;
 macro RCH$W_REMNI_HI = 4,0,16,0 %;
 macro RCH$B_CABLE = 6,0,8,0 %;
 macro RCH$B_MASK_XCH = 7,0,8,0 %;
 literal VC$M_WRK_SACK = 1;
 literal VC$M_WRK_SSEQ = 2;
 literal VC$M_WRK_ACXB = 4;
 literal VC$C_COUNTER_SIZE = 100;
 literal VC$M_OPEN = 1;
 literal VC$M_DQI = 2;
 literal VC$M_PATH = 4;
 literal VC$M_QUEUED = 8;
 literal VC$M_XSPRT = 16;
 literal VC$M_TIM_RXMT = 32;
 literal VC$M_PIPE_QUOTA = 64;
 literal VC$M_RWAIT = 128;
 literal VC$M_RESTART = 256;
*2I
*3D
 literal VC$c_QUE_NUMBER = 4;
*3E
*2E
*4I
*5I
 literal VC$M_DELAYD = 512;
*5E
 literal VC$c_QUE_NUMBER = 4;
*4E
 literal VC$M_MAINT_ID = 2147483647;
 literal VC$M_D = -2147483648;
 literal VC$M_M = 256;
 literal VC$M_PS = 1536;
 literal VC$M_SYS_STATE = -2048;
*5D
 literal VC$AZ_VEC1_RCH = 244;
 literal VC$C_LENGTH = 244;
 literal VC$S_VCDEF = 244;
*5E
*5I
 literal VC$AZ_VEC1_RCH = 260;
 literal VC$C_LENGTH = 260;
 literal VC$S_VCDEF = 260;
*5E
 macro VC$Q_QLNK = 0,0,0,0 %;
 literal VC$S_QLNK = 8;
 macro VC$W_SIZE = 8,0,16,0 %;
 macro VC$B_TYPE = 10,0,8,0 %;
 macro VC$B_WRK = 11,0,8,0 %;
 macro VC$V_WRK_SACK = 11,0,1,0 %;
 macro VC$V_WRK_SSEQ = 11,1,1,0 %;
 macro VC$V_WRK_ACXB = 11,2,1,0 %;
 macro VC$W_TIM_XACK = 12,0,16,0 %;
 macro VC$W_TIM_RACK = 14,0,16,0 %;
*5D
 macro VC$L_XMT_MSG = 16,0,32,0 %;
 macro VC$L_XMT_UNSEQ = 20,0,32,0 %;
 macro VC$L_XMT_SEQ = 24,0,32,0 %;
 macro VC$L_XMT_ACK = 28,0,32,0 %;
 macro VC$L_XMT_REXMT = 32,0,32,0 %;
 macro VC$L_XMT_CNTL = 36,0,32,0 %;
 macro VC$L_XMT_BYTES = 40,0,32,0 %;
 macro VC$L_XMT_NOXCH = 44,0,32,0 %;
 macro VC$L_RCV_MSG = 48,0,32,0 %;
 macro VC$L_RCV_UNSEQ = 52,0,32,0 %;
 macro VC$L_RCV_SEQ = 56,0,32,0 %;
 macro VC$L_RCV_ACK = 60,0,32,0 %;
 macro VC$L_RCV_RERCV = 64,0,32,0 %;
 macro VC$L_RCV_CNTL = 68,0,32,0 %;
 macro VC$L_RCV_BYTES = 72,0,32,0 %;
 macro VC$L_RCV_CACHE = 76,0,32,0 %;
 macro VC$W_HS_TMO = 80,0,16,0 %;
 macro VC$W_RCV_TR_SHORT = 82,0,16,0 %;
 macro VC$W_RCV_CC_SHORT = 84,0,16,0 %;
 macro VC$W_RCV_ILL_ACK = 86,0,16,0 %;
 macro VC$W_RCV_ILL_SEQ = 88,0,16,0 %;
 macro VC$W_RCV_BAD_CKSUM = 90,0,16,0 %;
 macro VC$W_RCV_NORCH = 92,0,16,0 %;
 macro VC$W_RCV_CC_BAD_ECO = 94,0,16,0 %;
 macro VC$W_RCV_CC_AUTHORIZE = 96,0,16,0 %;
 macro VC$W_RCV_CC_BAD_MC = 98,0,16,0 %;
 macro VC$W_XMT_SEQ_TMO = 100,0,16,0 %;
 macro VC$W_RCV_LISTEN_TMO = 102,0,16,0 %;
 macro VC$L_TR_PIPE_QUOTA = 104,0,32,0 %;
 macro VC$W_TR_DFQ_EMPTY = 108,0,16,0 %;
 macro VC$W_TR_MFQ_EMPTY = 110,0,16,0 %;
 macro VC$W_CC_DFQ_EMPTY = 112,0,16,0 %;
 macro VC$W_CC_MFQ_EMPTY = 114,0,16,0 %;
 macro VC$T_NODENAME = 116,0,0,0 %;
*5E
*5I
 macro VC$L_SAVE_RTN = 16,0,32,0 %;
 macro VC$L_SAVE_RCH = 20,0,32,0 %;
 macro VC$L_SAVE_BUS = 24,0,32,0 %;
 macro VC$L_SAVE_ACT_PTR = 28,0,32,0 %;
 macro VC$L_XMT_MSG = 32,0,32,0 %;
 macro VC$L_XMT_UNSEQ = 36,0,32,0 %;
 macro VC$L_XMT_SEQ = 40,0,32,0 %;
 macro VC$L_XMT_ACK = 44,0,32,0 %;
 macro VC$L_XMT_REXMT = 48,0,32,0 %;
 macro VC$L_XMT_CNTL = 52,0,32,0 %;
 macro VC$L_XMT_BYTES = 56,0,32,0 %;
 macro VC$L_XMT_NOXCH = 60,0,32,0 %;
 macro VC$L_RCV_MSG = 64,0,32,0 %;
 macro VC$L_RCV_UNSEQ = 68,0,32,0 %;
 macro VC$L_RCV_SEQ = 72,0,32,0 %;
 macro VC$L_RCV_ACK = 76,0,32,0 %;
 macro VC$L_RCV_RERCV = 80,0,32,0 %;
 macro VC$L_RCV_CNTL = 84,0,32,0 %;
 macro VC$L_RCV_BYTES = 88,0,32,0 %;
 macro VC$L_RCV_CACHE = 92,0,32,0 %;
 macro VC$W_HS_TMO = 96,0,16,0 %;
 macro VC$W_RCV_TR_SHORT = 98,0,16,0 %;
 macro VC$W_RCV_CC_SHORT = 100,0,16,0 %;
 macro VC$W_RCV_ILL_ACK = 102,0,16,0 %;
 macro VC$W_RCV_ILL_SEQ = 104,0,16,0 %;
 macro VC$W_RCV_BAD_CKSUM = 106,0,16,0 %;
 macro VC$W_RCV_NORCH = 108,0,16,0 %;
 macro VC$W_RCV_CC_BAD_ECO = 110,0,16,0 %;
 macro VC$W_RCV_CC_AUTHORIZE = 112,0,16,0 %;
 macro VC$W_RCV_CC_BAD_MC = 114,0,16,0 %;
 macro VC$W_XMT_SEQ_TMO = 116,0,16,0 %;
 macro VC$W_RCV_LISTEN_TMO = 118,0,16,0 %;
 macro VC$L_TR_PIPE_QUOTA = 120,0,32,0 %;
 macro VC$W_TR_DFQ_EMPTY = 124,0,16,0 %;
 macro VC$W_TR_MFQ_EMPTY = 126,0,16,0 %;
 macro VC$W_CC_DFQ_EMPTY = 128,0,16,0 %;
 macro VC$W_CC_MFQ_EMPTY = 130,0,16,0 %;
 macro VC$T_NODENAME = 132,0,0,0 %;
*5E
 literal VC$S_NODENAME = 8;
*5D
 macro VC$L_HASH_LINK = 124,0,32,0 %;
 macro VC$W_STS = 128,0,16,0 %;
 macro VC$V_OPEN = 128,0,1,0 %;
 macro VC$V_DQI = 128,1,1,0 %;
 macro VC$V_PATH = 128,2,1,0 %;
 macro VC$V_QUEUED = 128,3,1,0 %;
 macro VC$V_XSPRT = 128,4,1,0 %;
 macro VC$V_TIM_RXMT = 128,5,1,0 %;
 macro VC$V_PIPE_QUOTA = 128,6,1,0 %;
 macro VC$V_RWAIT = 128,7,1,0 %;
 macro VC$V_RESTART = 128,8,1,0 %;
 macro VC$B_TIME_RCH = 130,0,8,0 %;
 macro VC$B_MASK_RCH = 131,0,8,0 %;
 macro VC$L_REMSYS_LO = 132,0,32,0 %;
 macro VC$W_REMSYS_HI = 136,0,16,0 %;
 macro VC$B_PORT_INX = 138,0,8,0 %;
 macro VC$B_RETRIES = 139,0,8,0 %;
 macro VC$L_CXB_ACTION = 140,0,32,0 %;
 macro VC$L_CXB_RCV = 144,0,32,0 %;
 macro VC$L_CXB_FIRST = 148,0,32,0 %;
 macro VC$L_CXB_LAST = 152,0,32,0 %;
 macro VC$L_CXB_REXMT = 156,0,32,0 %;
 macro VC$W_LSX = 160,0,16,0 %;
 macro VC$W_HAA = 162,0,16,0 %;
 macro VC$W_LAR = 164,0,16,0 %;
 macro VC$W_HSR = 166,0,16,0 %;
 macro VC$W_NSU = 168,0,16,0 %;
 macro VC$W_RSVP_THRESH = 170,0,16,0 %;
 macro VC$B_PIPE_QUOTA = 172,0,8,0 %;
 macro VC$B_MASK_QUE = 173,0,8,0 %;
 macro VC$W_MAX_CMD_LEN = 174,0,16,0 %;
 macro VC$Q_RWAITQ = 176,0,0,0 %;
*5E
*5I
 macro VC$L_HASH_LINK = 140,0,32,0 %;
 macro VC$W_STS = 144,0,16,0 %;
 macro VC$V_OPEN = 144,0,1,0 %;
 macro VC$V_DQI = 144,1,1,0 %;
 macro VC$V_PATH = 144,2,1,0 %;
 macro VC$V_QUEUED = 144,3,1,0 %;
 macro VC$V_XSPRT = 144,4,1,0 %;
 macro VC$V_TIM_RXMT = 144,5,1,0 %;
 macro VC$V_PIPE_QUOTA = 144,6,1,0 %;
 macro VC$V_RWAIT = 144,7,1,0 %;
 macro VC$V_RESTART = 144,8,1,0 %;
 macro VC$V_DELAYD = 144,9,1,0 %;
 macro VC$B_TIME_RCH = 146,0,8,0 %;
 macro VC$B_MASK_RCH = 147,0,8,0 %;
 macro VC$L_REMSYS_LO = 148,0,32,0 %;
 macro VC$W_REMSYS_HI = 152,0,16,0 %;
 macro VC$B_PORT_INX = 154,0,8,0 %;
 macro VC$B_RETRIES = 155,0,8,0 %;
 macro VC$L_CXB_ACTION = 156,0,32,0 %;
 macro VC$L_CXB_RCV = 160,0,32,0 %;
 macro VC$L_CXB_FIRST = 164,0,32,0 %;
 macro VC$L_CXB_LAST = 168,0,32,0 %;
 macro VC$L_CXB_REXMT = 172,0,32,0 %;
 macro VC$W_LSX = 176,0,16,0 %;
 macro VC$W_HAA = 178,0,16,0 %;
 macro VC$W_LAR = 180,0,16,0 %;
 macro VC$W_HSR = 182,0,16,0 %;
 macro VC$W_NSU = 184,0,16,0 %;
 macro VC$W_RSVP_THRESH = 186,0,16,0 %;
 macro VC$B_PIPE_QUOTA = 188,0,8,0 %;
 macro VC$B_MASK_QUE = 189,0,8,0 %;
 macro VC$W_MAX_CMD_LEN = 190,0,16,0 %;
 macro VC$Q_RWAITQ = 192,0,0,0 %;
*5E
 literal VC$S_RWAITQ = 8;
*2D
 macro VC$Q_CMDQ0 = 184,0,0,0 %;
 literal VC$S_CMDQ0 = 8;
 macro VC$Q_CMDQ1 = 192,0,0,0 %;
 literal VC$S_CMDQ1 = 8;
 macro VC$Q_CMDQ2 = 200,0,0,0 %;
*2E
*2I
*3D
 macro VC$Q_CMDQ3 = 184,0,0,0 %;
 literal VC$S_CMDQ3 = 8;
 macro VC$Q_CMDQ2 = 192,0,0,0 %;
*3E
*3I
*4D
 macro VC$Q_CMDQ0 = 184,0,0,0 %;
 literal VC$S_CMDQ0 = 8;
 macro VC$Q_CMDQ1 = 192,0,0,0 %;
 literal VC$S_CMDQ1 = 8;
 macro VC$Q_CMDQ2 = 200,0,0,0 %;
*4E
*4I
*5D
 macro VC$Q_CMDQ3 = 184,0,0,0 %;
*5E
*5I
 macro VC$Q_CMDQ3 = 200,0,0,0 %;
*5E
 literal VC$S_CMDQ3 = 8;
*5D
 macro VC$Q_CMDQ2 = 192,0,0,0 %;
*5E
*5I
 macro VC$Q_CMDQ2 = 208,0,0,0 %;
*5E
*4E
*3E
*2E
 literal VC$S_CMDQ2 = 8;
*2D
 macro VC$Q_CMDQ3 = 208,0,0,0 %;
 literal VC$S_CMDQ3 = 8;
*2E
*2I
*3D
 macro VC$Q_CMDQHI = 200,0,0,0 %;
 literal VC$S_CMDQHI = 8;
 macro VC$Q_CMDQLO = 208,0,0,0 %;
 literal VC$S_CMDQLO = 8;
*3E
*3I
*4D
 macro VC$Q_CMDQ3 = 208,0,0,0 %;
 literal VC$S_CMDQ3 = 8;
*4E
*4I
*5D
 macro VC$Q_CMDQHI = 200,0,0,0 %;
*5E
*5I
 macro VC$Q_CMDQHI = 216,0,0,0 %;
*5E
 literal VC$S_CMDQHI = 8;
*5D
 macro VC$Q_CMDQLO = 208,0,0,0 %;
*5E
*5I
 macro VC$Q_CMDQLO = 224,0,0,0 %;
*5E
 literal VC$S_CMDQLO = 8;
*4E
*3E
*2E
*5D
 macro VC$W_CMDQ_LEN = 216,0,16,0 %;
 macro VC$W_FILL_1 = 218,0,16,0 %;
 macro VC$L_MAINT = 220,0,32,0 %;
 macro VC$V_MAINT_ID = 220,0,31,0 %;
*5E
*5I
 macro VC$W_CMDQ_LEN = 232,0,16,0 %;
 macro VC$W_FILL_1 = 234,0,16,0 %;
 macro VC$L_MAINT = 236,0,32,0 %;
 macro VC$V_MAINT_ID = 236,0,31,0 %;
*5E
 literal VC$S_MAINT_ID = 31;
*5D
 macro VC$V_D = 220,31,1,0 %;
 macro VC$B_MINOR = 224,0,8,0 %;
 macro VC$B_MAJOR = 225,0,8,0 %;
 macro VC$W_ECO = 226,0,16,0 %;
 macro VC$L_PORT_FCN = 228,0,32,0 %;
 macro VC$L_STA_INFO = 232,0,32,0 %;
 macro VC$V_M = 232,8,1,0 %;
 macro VC$V_PS = 232,9,2,0 %;
*5E
*5I
 macro VC$V_D = 236,31,1,0 %;
 macro VC$B_MINOR = 240,0,8,0 %;
 macro VC$B_MAJOR = 241,0,8,0 %;
 macro VC$W_ECO = 242,0,16,0 %;
 macro VC$L_PORT_FCN = 244,0,32,0 %;
 macro VC$L_STA_INFO = 248,0,32,0 %;
 macro VC$V_M = 248,8,1,0 %;
 macro VC$V_PS = 248,9,2,0 %;
*5E
 literal VC$S_PS = 2;
*5D
 macro VC$V_SYS_STATE = 232,11,21,0 %;
*5E
*5I
 macro VC$V_SYS_STATE = 248,11,21,0 %;
*5E
 literal VC$S_SYS_STATE = 21;
*5D
 macro VC$L_SRV = 236,0,32,0 %;
 macro VC$W_STATE = 240,0,16,0 %;
 macro VC$W_HS_TIMER = 242,0,16,0 %;
*5E
*5I
 macro VC$L_SRV = 252,0,32,0 %;
 macro VC$W_STATE = 256,0,16,0 %;
 macro VC$W_HS_TIMER = 258,0,16,0 %;
*5E
  
*2D
 !*** MODULE $PORTDEF ***
*2E
*2I
*3D
 !*** MODULE PORT ***
*3E
*3I
*4D
 !*** MODULE $PORTDEF ***
*4E
*4I
 !*** MODULE PORT ***
*4E
*3E
*2E
 literal RAIL$M_SHUT = 1;
 literal RAIL$C_LENGTH = 16;
 literal RAIL$S_RAILDEF = 16;
 macro RAIL$L_PTR_BUS = 0,0,32,0 %;
 macro RAIL$L_PTR_PORT = 4,0,32,0 %;
 macro RAIL$B_STS = 8,0,8,0 %;
 macro RAIL$V_SHUT = 8,0,1,0 %;
 macro RAIL$B_INDEX = 9,0,8,0 %;
 macro RAIL$B_TIM_HELLO = 10,0,8,0 %;
 macro RAIL$b_sp1 = 11,0,8,0 %;
 macro RAIL$L_PTR_BYE = 12,0,32,0 %;
*5D
 literal PORT$C_QUE_NUMBER = 7;
*5E
*5I
 literal PORT$C_INIT_LCXB_MAX = 256;
 literal PORT$C_INIT_SCXB_MAX = 512;
 literal PORT$C_INIT_LCXB_QUO = 1;
 literal PORT$C_INIT_SCXB_QUO = 8;
 literal PORT$C_SCXB_QUO_INCR = 1;
 literal PORT$C_QUE_NUMBER = 8;
*5E
 literal PORT$M_AUTHORIZE = 1;
 literal PORT$M_FORK = 2;
 literal PORT$M_NEED_LCXB = 4;
 literal PORT$M_NEED_SCXB = 8;
 literal PORT$M_NEED_MFQ = 16;
 literal PORT$M_NEED_DFQ = 32;
 literal PORT$M_DISABLED = 64;
 literal PORT$M_SYNCH = 128;
 literal PORT$M_WRK_RWAITQ = 1;
 literal PORT$M_WRK_VCQ = 2;
*2D
 literal PORT$M_WRK_CMDQ = 4;
 literal PORT$M_WRK_INTR = 8;
 literal PORT$M_WRK_LDL = 16;
 literal PORT$M_WRK_TIMER = 32;
*2E
*2I
*3D
 literal PORT$M_WRK_INTR = 4;
 literal PORT$M_WRK_LDL = 8;
 literal PORT$M_WRK_TIMER = 16;
*3E
*3I
*4D
 literal PORT$M_WRK_CMDQ = 4;
 literal PORT$M_WRK_INTR = 8;
 literal PORT$M_WRK_LDL = 16;
 literal PORT$M_WRK_TIMER = 32;
*4E
*4I
 literal PORT$M_WRK_INTR = 4;
 literal PORT$M_WRK_LDL = 8;
 literal PORT$M_WRK_TIMER = 16;
*4E
*3E
*2E
*5D
 literal PORT$C_MIN_LCXB = 42;
 literal PORT$C_MIN_SCXB = 60;
*5E
*2I
*3D
 literal PORT$C_PORT_COUNTER_SIZE = 100;
*3E
*2E
*4I
 literal PORT$C_PORT_COUNTER_SIZE = 100;
*4E
 literal PORT$C_ERRLOG_THRES = 10;
 literal PORT$C_ERR_RATE_INT = 3;
 literal PORT$M_MAINT_ID = 2147483647;
 literal PORT$M_D = -2147483648;
 literal PORT$M_M = 256;
 literal PORT$M_PS = 1536;
 literal PORT$M_SYS_STATE = -2048;
 literal PORT$C_RAIL_MAX = 8;
 literal PORT$C_VC_MAX = 256;
 literal PORT$V_HASH = 32;
 literal PORT$S_HASH = 4;
*2D
 literal PORT$C_LENGTH = 496;
 literal PORT$S_PORTDEF = 496;
*2E
*2I
*3D
 literal PORT$C_LENGTH = 500;
 literal PORT$S_PORTDEF = 500;
*3E
*3I
*4D
 literal PORT$C_LENGTH = 496;
 literal PORT$S_PORTDEF = 496;
*4E
*4I
*5D
 literal PORT$C_LENGTH = 500;
 literal PORT$S_PORTDEF = 500;
*5E
*5I
 literal PORT$C_LENGTH = 532;
 literal PORT$S_PORTDEF = 532;
*5E
*4E
*3E
*2E
 macro PORT$Q_FORK = 0,0,0,0 %;
 literal PORT$S_FORK = 8;
 macro PORT$W_SIZE = 8,0,16,0 %;
 macro PORT$B_TYPE = 10,0,8,0 %;
 macro PORT$B_FLCK = 11,0,8,0 %;
 macro PORT$L_FPC = 12,0,32,0 %;
 macro PORT$L_FR3 = 16,0,32,0 %;
 macro PORT$L_FR4 = 20,0,32,0 %;
 macro PORT$Q_QUE_FIRST = 24,0,0,0 %;
 literal PORT$S_QUE_FIRST = 8;
 macro PORT$Q_VC_WORK = 24,0,0,0 %;
 literal PORT$S_VC_WORK = 8;
 macro PORT$Q_SCXB_FREE = 32,0,0,0 %;
 literal PORT$S_SCXB_FREE = 8;
 macro PORT$Q_LCXB_FREE = 40,0,0,0 %;
 literal PORT$S_LCXB_FREE = 8;
 macro PORT$Q_DFQ = 48,0,0,0 %;
 literal PORT$S_DFQ = 8;
 macro PORT$Q_MFQ = 56,0,0,0 %;
 literal PORT$S_MFQ = 8;
 macro PORT$Q_CXB_LDL = 64,0,0,0 %;
 literal PORT$S_CXB_LDL = 8;
 macro PORT$Q_RWAITQ = 72,0,0,0 %;
 literal PORT$S_RWAITQ = 8;
*5D
 macro PORT$W_STS = 80,0,16,0 %;
 macro PORT$V_AUTHORIZE = 80,0,1,0 %;
 macro PORT$V_FORK = 80,1,1,0 %;
 macro PORT$V_NEED_LCXB = 80,2,1,0 %;
 macro PORT$V_NEED_SCXB = 80,3,1,0 %;
 macro PORT$V_NEED_MFQ = 80,4,1,0 %;
 macro PORT$V_NEED_DFQ = 80,5,1,0 %;
 macro PORT$V_DISABLED = 80,6,1,0 %;
 macro PORT$V_SYNCH = 80,7,1,0 %;
 macro PORT$W_CLOCK = 82,0,16,0 %;
 macro PORT$L_SECS_ZEROED = 84,0,32,0 %;
*5E
*2D
 macro PORT$W_PCI_SCXB_EMPTY = 88,0,16,0 %;
 macro PORT$W_PCI_LCXB_EMPTY = 90,0,16,0 %;
 macro PORT$W_TR_SCXB_EMPTY = 92,0,16,0 %;
 macro PORT$W_FILL_0 = 94,0,16,0 %;
 macro PORT$B_RAIL_NUM = 96,0,8,0 %;
 macro PORT$B_VC_NUM = 97,0,8,0 %;
 macro PORT$B_VC_CNT = 98,0,8,0 %;
 macro PORT$B_VC_LAST = 99,0,8,0 %;
 macro PORT$L_PTR_PORTQB = 100,0,32,0 %;
 macro PORT$L_INTR_SRV = 104,0,32,0 %;
 macro PORT$Q_AUTHORIZE = 108,0,0,0 %;
*2E
*2I
*3D
 macro PORT$B_RAIL_NUM = 88,0,8,0 %;
 macro PORT$B_VC_NUM = 89,0,8,0 %;
 macro PORT$B_VC_CNT = 90,0,8,0 %;
 macro PORT$B_VC_LAST = 91,0,8,0 %;
 macro PORT$L_PTR_PORTQB = 92,0,32,0 %;
 macro PORT$L_INTR_SRV = 96,0,32,0 %;
 macro PORT$Q_AUTHORIZE = 100,0,0,0 %;
*3E
*3I
*4D
 macro PORT$W_PCI_SCXB_EMPTY = 88,0,16,0 %;
 macro PORT$W_PCI_LCXB_EMPTY = 90,0,16,0 %;
 macro PORT$W_TR_SCXB_EMPTY = 92,0,16,0 %;
 macro PORT$W_FILL_0 = 94,0,16,0 %;
 macro PORT$B_RAIL_NUM = 96,0,8,0 %;
 macro PORT$B_VC_NUM = 97,0,8,0 %;
 macro PORT$B_VC_CNT = 98,0,8,0 %;
 macro PORT$B_VC_LAST = 99,0,8,0 %;
 macro PORT$L_PTR_PORTQB = 100,0,32,0 %;
 macro PORT$L_INTR_SRV = 104,0,32,0 %;
 macro PORT$Q_AUTHORIZE = 108,0,0,0 %;
*4E
*4I
*5D
 macro PORT$B_RAIL_NUM = 88,0,8,0 %;
 macro PORT$B_VC_NUM = 89,0,8,0 %;
 macro PORT$B_VC_CNT = 90,0,8,0 %;
 macro PORT$B_VC_LAST = 91,0,8,0 %;
 macro PORT$L_PTR_PORTQB = 92,0,32,0 %;
 macro PORT$L_INTR_SRV = 96,0,32,0 %;
 macro PORT$Q_AUTHORIZE = 100,0,0,0 %;
*5E
*5I
 macro PORT$Q_DELAYQ = 80,0,0,0 %;
 literal PORT$S_DELAYQ = 8;
 macro PORT$W_STS = 88,0,16,0 %;
 macro PORT$V_AUTHORIZE = 88,0,1,0 %;
 macro PORT$V_FORK = 88,1,1,0 %;
 macro PORT$V_NEED_LCXB = 88,2,1,0 %;
 macro PORT$V_NEED_SCXB = 88,3,1,0 %;
 macro PORT$V_NEED_MFQ = 88,4,1,0 %;
 macro PORT$V_NEED_DFQ = 88,5,1,0 %;
 macro PORT$V_DISABLED = 88,6,1,0 %;
 macro PORT$V_SYNCH = 88,7,1,0 %;
 macro PORT$W_CLOCK = 90,0,16,0 %;
 macro PORT$L_SECS_ZEROED = 92,0,32,0 %;
 macro PORT$B_RAIL_NUM = 96,0,8,0 %;
 macro PORT$B_VC_NUM = 97,0,8,0 %;
 macro PORT$B_VC_CNT = 98,0,8,0 %;
 macro PORT$B_VC_LAST = 99,0,8,0 %;
 macro PORT$L_PTR_PORTQB = 100,0,32,0 %;
 macro PORT$L_INTR_SRV = 104,0,32,0 %;
 macro PORT$Q_AUTHORIZE = 108,0,0,0 %;
*5E
*4E
*3E
*2E
 literal PORT$S_AUTHORIZE = 8;
*2D
 macro PORT$L_SERVICES = 116,0,32,0 %;
 macro PORT$W_MAX_LNGMSG = 120,0,16,0 %;
 macro PORT$W_MAX_LNGDG = 122,0,16,0 %;
 macro PORT$L_PTR_VCVEC0 = 124,0,32,0 %;
 macro PORT$W_DELAY_ACK = 128,0,16,0 %;
 macro PORT$W_DELAY_SEQ = 130,0,16,0 %;
 macro PORT$W_DELAY_XSPRT = 132,0,16,0 %;
 macro PORT$B_FILL1 = 134,0,8,0 %;
 macro PORT$B_MAX_CACHE = 135,0,8,0 %;
 macro PORT$B_MAX_REXMT = 136,0,8,0 %;
 macro PORT$B_NUM_RCH = 137,0,8,0 %;
 macro PORT$W_WRK = 138,0,16,0 %;
 macro PORT$V_WRK_RWAITQ = 138,0,1,0 %;
 macro PORT$V_WRK_VCQ = 138,1,1,0 %;
 macro PORT$V_WRK_CMDQ = 138,2,1,0 %;
 macro PORT$V_WRK_INTR = 138,3,1,0 %;
 macro PORT$V_WRK_LDL = 138,4,1,0 %;
 macro PORT$V_WRK_TIMER = 138,5,1,0 %;
 macro PORT$T_NODENAME = 140,0,0,0 %;
*2E
*2I
*3D
 macro PORT$L_SERVICES = 108,0,32,0 %;
 macro PORT$W_MAX_LNGMSG = 112,0,16,0 %;
 macro PORT$W_MAX_LNGDG = 114,0,16,0 %;
 macro PORT$L_PTR_VCVEC0 = 116,0,32,0 %;
 macro PORT$W_DELAY_ACK = 120,0,16,0 %;
 macro PORT$W_DELAY_SEQ = 122,0,16,0 %;
 macro PORT$W_DELAY_XSPRT = 124,0,16,0 %;
 macro PORT$B_FILL1 = 126,0,8,0 %;
 macro PORT$B_MAX_CACHE = 127,0,8,0 %;
 macro PORT$B_MAX_REXMT = 128,0,8,0 %;
 macro PORT$B_NUM_RCH = 129,0,8,0 %;
 macro PORT$W_WRK = 130,0,16,0 %;
 macro PORT$V_WRK_RWAITQ = 130,0,1,0 %;
 macro PORT$V_WRK_VCQ = 130,1,1,0 %;
 macro PORT$V_WRK_INTR = 130,2,1,0 %;
 macro PORT$V_WRK_LDL = 130,3,1,0 %;
 macro PORT$V_WRK_TIMER = 130,4,1,0 %;
 macro PORT$T_NODENAME = 132,0,0,0 %;
*3E
*3I
*4D
 macro PORT$L_SERVICES = 116,0,32,0 %;
 macro PORT$W_MAX_LNGMSG = 120,0,16,0 %;
 macro PORT$W_MAX_LNGDG = 122,0,16,0 %;
 macro PORT$L_PTR_VCVEC0 = 124,0,32,0 %;
 macro PORT$W_DELAY_ACK = 128,0,16,0 %;
 macro PORT$W_DELAY_SEQ = 130,0,16,0 %;
 macro PORT$W_DELAY_XSPRT = 132,0,16,0 %;
 macro PORT$B_FILL1 = 134,0,8,0 %;
 macro PORT$B_MAX_CACHE = 135,0,8,0 %;
 macro PORT$B_MAX_REXMT = 136,0,8,0 %;
 macro PORT$B_NUM_RCH = 137,0,8,0 %;
 macro PORT$W_WRK = 138,0,16,0 %;
 macro PORT$V_WRK_RWAITQ = 138,0,1,0 %;
 macro PORT$V_WRK_VCQ = 138,1,1,0 %;
 macro PORT$V_WRK_CMDQ = 138,2,1,0 %;
 macro PORT$V_WRK_INTR = 138,3,1,0 %;
 macro PORT$V_WRK_LDL = 138,4,1,0 %;
 macro PORT$V_WRK_TIMER = 138,5,1,0 %;
 macro PORT$T_NODENAME = 140,0,0,0 %;
*4E
*4I
*5D
 macro PORT$L_SERVICES = 108,0,32,0 %;
 macro PORT$W_MAX_LNGMSG = 112,0,16,0 %;
 macro PORT$W_MAX_LNGDG = 114,0,16,0 %;
 macro PORT$L_PTR_VCVEC0 = 116,0,32,0 %;
 macro PORT$W_DELAY_ACK = 120,0,16,0 %;
 macro PORT$W_DELAY_SEQ = 122,0,16,0 %;
 macro PORT$W_DELAY_XSPRT = 124,0,16,0 %;
 macro PORT$B_FILL1 = 126,0,8,0 %;
 macro PORT$B_MAX_CACHE = 127,0,8,0 %;
 macro PORT$B_MAX_REXMT = 128,0,8,0 %;
 macro PORT$B_NUM_RCH = 129,0,8,0 %;
 macro PORT$W_WRK = 130,0,16,0 %;
 macro PORT$V_WRK_RWAITQ = 130,0,1,0 %;
 macro PORT$V_WRK_VCQ = 130,1,1,0 %;
 macro PORT$V_WRK_INTR = 130,2,1,0 %;
 macro PORT$V_WRK_LDL = 130,3,1,0 %;
 macro PORT$V_WRK_TIMER = 130,4,1,0 %;
 macro PORT$T_NODENAME = 132,0,0,0 %;
*5E
*5I
 macro PORT$L_SERVICES = 116,0,32,0 %;
 macro PORT$W_MAX_LNGMSG = 120,0,16,0 %;
 macro PORT$W_MAX_LNGDG = 122,0,16,0 %;
 macro PORT$L_PTR_VCVEC0 = 124,0,32,0 %;
 macro PORT$W_DELAY_ACK = 128,0,16,0 %;
 macro PORT$W_DELAY_SEQ = 130,0,16,0 %;
 macro PORT$W_DELAY_XSPRT = 132,0,16,0 %;
 macro PORT$B_FILL1 = 134,0,8,0 %;
 macro PORT$B_MAX_CACHE = 135,0,8,0 %;
 macro PORT$B_MAX_REXMT = 136,0,8,0 %;
 macro PORT$B_NUM_RCH = 137,0,8,0 %;
 macro PORT$W_WRK = 138,0,16,0 %;
 macro PORT$V_WRK_RWAITQ = 138,0,1,0 %;
 macro PORT$V_WRK_VCQ = 138,1,1,0 %;
 macro PORT$V_WRK_INTR = 138,2,1,0 %;
 macro PORT$V_WRK_LDL = 138,3,1,0 %;
 macro PORT$V_WRK_TIMER = 138,4,1,0 %;
 macro PORT$T_NODENAME = 140,0,0,0 %;
*5E
*4E
*3E
*2E
 literal PORT$S_NODENAME = 8;
*2D
 macro PORT$B_SCXB_CNT = 148,0,8,0 %;
 macro PORT$B_SCXB_MAX = 149,0,8,0 %;
 macro PORT$W_SCXB_SIZE = 150,0,16,0 %;
 macro PORT$B_LCXB_CNT = 152,0,8,0 %;
 macro PORT$B_LCXB_MAX = 153,0,8,0 %;
 macro PORT$W_LCXB_SIZE = 154,0,16,0 %;
 macro PORT$B_SCAN_XACK = 156,0,8,0 %;
 macro PORT$B_SCAN_XSEQ = 157,0,8,0 %;
 macro PORT$B_SCAN_SCXB = 158,0,8,0 %;
 macro PORT$B_NEED_SACK = 159,0,8,0 %;
 macro PORT$L_LINK = 160,0,32,0 %;
 macro PORT$L_SYSID_LO = 164,0,32,0 %;
 macro PORT$W_SYSID_HI = 168,0,16,0 %;
 macro PORT$W_GROUP = 170,0,16,0 %;
 macro PORT$B_PIPE_QUOTA = 172,0,8,0 %;
 macro PORT$B_TIM_ERR_LOG = 173,0,8,0 %;
 macro PORT$W_FILL_2 = 174,0,16,0 %;
 macro PORT$L_MCAST_LO = 176,0,32,0 %;
 macro PORT$W_MCAST_HI = 180,0,16,0 %;
 macro PORT$B_MASK_QUE = 182,0,8,0 %;
 macro PORT$B_MASK_HELLO = 183,0,8,0 %;
 macro PORT$L_MAINT = 184,0,32,0 %;
 macro PORT$V_MAINT_ID = 184,0,31,0 %;
*2E
*2I
*3D
 macro PORT$B_SCXB_CNT = 140,0,8,0 %;
 macro PORT$B_SCXB_MAX = 141,0,8,0 %;
 macro PORT$W_SCXB_SIZE = 142,0,16,0 %;
 macro PORT$B_LCXB_CNT = 144,0,8,0 %;
 macro PORT$B_LCXB_MAX = 145,0,8,0 %;
 macro PORT$W_LCXB_SIZE = 146,0,16,0 %;
 macro PORT$B_SCXB_INUSE_CNT = 148,0,8,0 %;
 macro PORT$B_SCXB_INUSE_PEAK = 149,0,8,0 %;
 macro PORT$B_LCXB_INUSE_CNT = 150,0,8,0 %;
 macro PORT$B_LCXB_INUSE_PEAK = 151,0,8,0 %;
 macro PORT$W_PCI_SCXB_EMPTY = 152,0,16,0 %;
 macro PORT$W_PCI_LCXB_EMPTY = 154,0,16,0 %;
 macro PORT$W_TR_SCXB_EMPTY = 156,0,16,0 %;
 macro PORT$W_FILL_0 = 158,0,16,0 %;
 macro PORT$B_SCAN_XACK = 160,0,8,0 %;
 macro PORT$B_SCAN_XSEQ = 161,0,8,0 %;
 macro PORT$B_SCAN_SCXB = 162,0,8,0 %;
 macro PORT$B_NEED_SACK = 163,0,8,0 %;
 macro PORT$L_LINK = 164,0,32,0 %;
 macro PORT$L_SYSID_LO = 168,0,32,0 %;
 macro PORT$W_SYSID_HI = 172,0,16,0 %;
 macro PORT$W_GROUP = 174,0,16,0 %;
 macro PORT$B_PIPE_QUOTA = 176,0,8,0 %;
 macro PORT$B_TIM_ERR_LOG = 177,0,8,0 %;
 macro PORT$W_FILL_2 = 178,0,16,0 %;
 macro PORT$L_MCAST_LO = 180,0,32,0 %;
 macro PORT$W_MCAST_HI = 184,0,16,0 %;
 macro PORT$B_MASK_HELLO = 187,0,8,0 %;
 macro PORT$L_MAINT = 188,0,32,0 %;
 macro PORT$V_MAINT_ID = 188,0,31,0 %;
*3E
*3I
*4D
 macro PORT$B_SCXB_CNT = 148,0,8,0 %;
 macro PORT$B_SCXB_MAX = 149,0,8,0 %;
 macro PORT$W_SCXB_SIZE = 150,0,16,0 %;
 macro PORT$B_LCXB_CNT = 152,0,8,0 %;
 macro PORT$B_LCXB_MAX = 153,0,8,0 %;
 macro PORT$W_LCXB_SIZE = 154,0,16,0 %;
 macro PORT$B_SCAN_XACK = 156,0,8,0 %;
 macro PORT$B_SCAN_XSEQ = 157,0,8,0 %;
 macro PORT$B_SCAN_SCXB = 158,0,8,0 %;
 macro PORT$B_NEED_SACK = 159,0,8,0 %;
 macro PORT$L_LINK = 160,0,32,0 %;
 macro PORT$L_SYSID_LO = 164,0,32,0 %;
 macro PORT$W_SYSID_HI = 168,0,16,0 %;
 macro PORT$W_GROUP = 170,0,16,0 %;
 macro PORT$B_PIPE_QUOTA = 172,0,8,0 %;
 macro PORT$B_TIM_ERR_LOG = 173,0,8,0 %;
 macro PORT$W_FILL_2 = 174,0,16,0 %;
 macro PORT$L_MCAST_LO = 176,0,32,0 %;
 macro PORT$W_MCAST_HI = 180,0,16,0 %;
 macro PORT$B_MASK_QUE = 182,0,8,0 %;
 macro PORT$B_MASK_HELLO = 183,0,8,0 %;
 macro PORT$L_MAINT = 184,0,32,0 %;
 macro PORT$V_MAINT_ID = 184,0,31,0 %;
*4E
*4I
*5D
 macro PORT$B_SCXB_CNT = 140,0,8,0 %;
 macro PORT$B_SCXB_MAX = 141,0,8,0 %;
 macro PORT$W_SCXB_SIZE = 142,0,16,0 %;
 macro PORT$B_LCXB_CNT = 144,0,8,0 %;
 macro PORT$B_LCXB_MAX = 145,0,8,0 %;
 macro PORT$W_LCXB_SIZE = 146,0,16,0 %;
 macro PORT$B_SCXB_INUSE_CNT = 148,0,8,0 %;
 macro PORT$B_SCXB_INUSE_PEAK = 149,0,8,0 %;
 macro PORT$B_LCXB_INUSE_CNT = 150,0,8,0 %;
 macro PORT$B_LCXB_INUSE_PEAK = 151,0,8,0 %;
 macro PORT$W_PCI_SCXB_EMPTY = 152,0,16,0 %;
 macro PORT$W_PCI_LCXB_EMPTY = 154,0,16,0 %;
 macro PORT$W_TR_SCXB_EMPTY = 156,0,16,0 %;
 macro PORT$W_FILL_0 = 158,0,16,0 %;
 macro PORT$B_SCAN_XACK = 160,0,8,0 %;
 macro PORT$B_SCAN_XSEQ = 161,0,8,0 %;
 macro PORT$B_SCAN_SCXB = 162,0,8,0 %;
 macro PORT$B_NEED_SACK = 163,0,8,0 %;
 macro PORT$L_LINK = 164,0,32,0 %;
 macro PORT$L_SYSID_LO = 168,0,32,0 %;
 macro PORT$W_SYSID_HI = 172,0,16,0 %;
 macro PORT$W_GROUP = 174,0,16,0 %;
 macro PORT$B_PIPE_QUOTA = 176,0,8,0 %;
 macro PORT$B_TIM_ERR_LOG = 177,0,8,0 %;
 macro PORT$W_FILL_2 = 178,0,16,0 %;
 macro PORT$L_MCAST_LO = 180,0,32,0 %;
 macro PORT$W_MCAST_HI = 184,0,16,0 %;
 macro PORT$B_MASK_HELLO = 187,0,8,0 %;
 macro PORT$L_MAINT = 188,0,32,0 %;
 macro PORT$V_MAINT_ID = 188,0,31,0 %;
*5E
*5I
 macro PORT$W_SCXB_SIZE = 148,0,16,0 %;
 macro PORT$W_LCXB_SIZE = 150,0,16,0 %;
 macro PORT$W_SCXB_CNT = 152,0,16,0 %;
 macro PORT$W_SCXB_QUO = 154,0,16,0 %;
 macro PORT$W_SCXB_MAX = 156,0,16,0 %;
 macro PORT$W_LCXB_CNT = 158,0,16,0 %;
 macro PORT$W_LCXB_QUO = 160,0,16,0 %;
 macro PORT$W_LCXB_MAX = 162,0,16,0 %;
 macro PORT$L_TOT_LCXB_ALLOCS = 164,0,32,0 %;
 macro PORT$L_TOT_SCXB_ALLOCS = 168,0,32,0 %;
 macro PORT$W_LCXB_LOOKASIDE_MISS = 172,0,16,0 %;
 macro PORT$W_SCXB_LOOKASIDE_MISS = 174,0,16,0 %;
 macro PORT$W_SCXB_INUSE_CNT = 176,0,16,0 %;
 macro PORT$W_SCXB_INUSE_PEAK = 178,0,16,0 %;
 macro PORT$W_LCXB_INUSE_CNT = 180,0,16,0 %;
 macro PORT$W_LCXB_INUSE_PEAK = 182,0,16,0 %;
 macro PORT$W_PCI_SCXB_EMPTY = 184,0,16,0 %;
 macro PORT$W_PCI_LCXB_EMPTY = 186,0,16,0 %;
 macro PORT$W_TR_SCXB_EMPTY = 188,0,16,0 %;
 macro PORT$W_FILL_0 = 190,0,16,0 %;
 macro PORT$B_SCAN_XACK = 192,0,8,0 %;
 macro PORT$B_SCAN_XSEQ = 193,0,8,0 %;
 macro PORT$B_SCAN_SCXB = 194,0,8,0 %;
 macro PORT$B_NEED_SACK = 195,0,8,0 %;
 macro PORT$L_LINK = 196,0,32,0 %;
 macro PORT$L_SYSID_LO = 200,0,32,0 %;
 macro PORT$W_SYSID_HI = 204,0,16,0 %;
 macro PORT$W_GROUP = 206,0,16,0 %;
 macro PORT$B_PIPE_QUOTA = 208,0,8,0 %;
 macro PORT$B_TIM_ERR_LOG = 209,0,8,0 %;
 macro PORT$W_FILL_2 = 210,0,16,0 %;
 macro PORT$L_MCAST_LO = 212,0,32,0 %;
 macro PORT$W_MCAST_HI = 216,0,16,0 %;
 macro PORT$B_MASK_HELLO = 219,0,8,0 %;
 macro PORT$L_MAINT = 220,0,32,0 %;
 macro PORT$V_MAINT_ID = 220,0,31,0 %;
*5E
*4E
*3E
*2E
 literal PORT$S_MAINT_ID = 31;
*2D
 macro PORT$V_D = 184,31,1,0 %;
 macro PORT$B_MINOR = 188,0,8,0 %;
 macro PORT$B_MAJOR = 189,0,8,0 %;
 macro PORT$W_ECO = 190,0,16,0 %;
 macro PORT$L_PORT_FCN = 192,0,32,0 %;
 macro PORT$L_STA_INFO = 196,0,32,0 %;
 macro PORT$V_M = 196,8,1,0 %;
 macro PORT$V_PS = 196,9,2,0 %;
*2E
*2I
*3D
 macro PORT$V_D = 188,31,1,0 %;
 macro PORT$B_MINOR = 192,0,8,0 %;
 macro PORT$B_MAJOR = 193,0,8,0 %;
 macro PORT$W_ECO = 194,0,16,0 %;
 macro PORT$L_PORT_FCN = 196,0,32,0 %;
 macro PORT$L_STA_INFO = 200,0,32,0 %;
 macro PORT$V_M = 200,8,1,0 %;
 macro PORT$V_PS = 200,9,2,0 %;
*3E
*3I
*4D
 macro PORT$V_D = 184,31,1,0 %;
 macro PORT$B_MINOR = 188,0,8,0 %;
 macro PORT$B_MAJOR = 189,0,8,0 %;
 macro PORT$W_ECO = 190,0,16,0 %;
 macro PORT$L_PORT_FCN = 192,0,32,0 %;
 macro PORT$L_STA_INFO = 196,0,32,0 %;
 macro PORT$V_M = 196,8,1,0 %;
 macro PORT$V_PS = 196,9,2,0 %;
*4E
*4I
*5D
 macro PORT$V_D = 188,31,1,0 %;
 macro PORT$B_MINOR = 192,0,8,0 %;
 macro PORT$B_MAJOR = 193,0,8,0 %;
 macro PORT$W_ECO = 194,0,16,0 %;
 macro PORT$L_PORT_FCN = 196,0,32,0 %;
 macro PORT$L_STA_INFO = 200,0,32,0 %;
 macro PORT$V_M = 200,8,1,0 %;
 macro PORT$V_PS = 200,9,2,0 %;
*5E
*5I
 macro PORT$V_D = 220,31,1,0 %;
 macro PORT$B_MINOR = 224,0,8,0 %;
 macro PORT$B_MAJOR = 225,0,8,0 %;
 macro PORT$W_ECO = 226,0,16,0 %;
 macro PORT$L_PORT_FCN = 228,0,32,0 %;
 macro PORT$L_STA_INFO = 232,0,32,0 %;
 macro PORT$V_M = 232,8,1,0 %;
 macro PORT$V_PS = 232,9,2,0 %;
*5E
*4E
*3E
*2E
 literal PORT$S_PS = 2;
*2D
 macro PORT$V_SYS_STATE = 196,11,21,0 %;
*2E
*2I
*3D
 macro PORT$V_SYS_STATE = 200,11,21,0 %;
*3E
*3I
*4D
 macro PORT$V_SYS_STATE = 196,11,21,0 %;
*4E
*4I
*5D
 macro PORT$V_SYS_STATE = 200,11,21,0 %;
*5E
*5I
 macro PORT$V_SYS_STATE = 232,11,21,0 %;
*5E
*4E
*3E
*2E
 literal PORT$S_SYS_STATE = 21;
*2D
 macro PORT$T_RST_PORT = 200,0,0,0 %;
*2E
*2I
*3D
 macro PORT$T_RST_PORT = 204,0,0,0 %;
*3E
*3I
*4D
 macro PORT$T_RST_PORT = 200,0,0,0 %;
*4E
*4I
*5D
 macro PORT$T_RST_PORT = 204,0,0,0 %;
*5E
*5I
 macro PORT$T_RST_PORT = 236,0,0,0 %;
*5E
*4E
*3E
*2E
 literal PORT$S_RST_PORT = 6;
*2D
 macro PORT$T_MASK_SCXB = 208,0,0,0 %;
*2E
*2I
*3D
 macro PORT$T_MASK_SCXB = 212,0,0,0 %;
*3E
*3I
*4D
 macro PORT$T_MASK_SCXB = 208,0,0,0 %;
*4E
*4I
*5D
 macro PORT$T_MASK_SCXB = 212,0,0,0 %;
*5E
*5I
 macro PORT$T_MASK_SCXB = 244,0,0,0 %;
*5E
*4E
*3E
*2E
 literal PORT$S_MASK_SCXB = 32;
*2D
 macro PORT$T_MASK_XACK = 240,0,0,0 %;
*2E
*2I
*3D
 macro PORT$T_MASK_XACK = 244,0,0,0 %;
*3E
*3I
*4D
 macro PORT$T_MASK_XACK = 240,0,0,0 %;
*4E
*4I
*5D
 macro PORT$T_MASK_XACK = 244,0,0,0 %;
*5E
*5I
 macro PORT$T_MASK_XACK = 276,0,0,0 %;
*5E
*4E
*3E
*2E
 literal PORT$S_MASK_XACK = 32;
*2D
 macro PORT$T_MASK_XSEQ = 272,0,0,0 %;
*2E
*2I
*3D
 macro PORT$T_MASK_XSEQ = 276,0,0,0 %;
*3E
*3I
*4D
 macro PORT$T_MASK_XSEQ = 272,0,0,0 %;
*4E
*4I
*5D
 macro PORT$T_MASK_XSEQ = 276,0,0,0 %;
*5E
*5I
 macro PORT$T_MASK_XSEQ = 308,0,0,0 %;
*5E
*4E
*3E
*2E
 literal PORT$S_MASK_XSEQ = 32;
*2D
 macro PORT$AZ_VEC0_RAIL = 304,0,0,0 %;
*2E
*2I
*3D
 macro PORT$AZ_VEC0_RAIL = 308,0,0,0 %;
*3E
*3I
*4D
 macro PORT$AZ_VEC0_RAIL = 304,0,0,0 %;
*4E
*4I
*5D
 macro PORT$AZ_VEC0_RAIL = 308,0,0,0 %;
*5E
*5I
 macro PORT$AZ_VEC0_RAIL = 340,0,0,0 %;
*5E
*4E
*3E
*2E
 literal PORT$S_VEC0_RAIL = 128;
*2D
 macro PORT$AL_VEC0_HASH = 432,0,0,0 %;
*2E
*2I
*3D
 macro PORT$AL_VEC0_HASH = 436,0,0,0 %;
*3E
*3I
*4D
 macro PORT$AL_VEC0_HASH = 432,0,0,0 %;
*4E
*4I
*5D
 macro PORT$AL_VEC0_HASH = 436,0,0,0 %;
*5E
*5I
 macro PORT$AL_VEC0_HASH = 468,0,0,0 %;
*5E
*4E
*3E
*2E
 literal PORT$S_VEC0_HASH = 64;
  
*2D
 !*** MODULE $ROOTDEF ***
*2E
*2I
*3D
 !*** MODULE ROOT ***
*3E
*3I
*4D
 !*** MODULE $ROOTDEF ***
*4E
*4I
 !*** MODULE ROOT ***
*4E
*3E
*2E
 literal ROOT$C_LENGTH = 24;
 literal ROOT$S_ROOTDEF = 24;
 macro ROOT$L_LIST_BUS = 0,0,32,0 %;
 macro ROOT$L_LIST_PORT = 4,0,32,0 %;
 macro ROOT$W_SIZE = 8,0,16,0 %;
 macro ROOT$B_TYPE = 10,0,8,0 %;
 macro ROOT$L_INX_SPT0 = 12,0,32,0 %;
 macro ROOT$L_SVA = 16,0,32,0 %;
 macro ROOT$L_PTR_PTE0 = 20,0,32,0 %;
 macro ROOT$T_TQE = 24,0,0,0 %;
  
*2D
 !*** MODULE $CCDEF ***
*2E
*2I
*3D
 !*** MODULE CC ***
*3E
*3I
*4D
 !*** MODULE $CCDEF ***
*4E
*4I
 !*** MODULE CC ***
*4E
*3E
*2E
 literal CC$C_EVT_HELLO = 0;
 literal CC$C_EVT_BYE = 1;
 literal CC$C_EVT_CCSTART = 2;
 literal CC$C_EVT_VERF = 3;
 literal CC$C_EVT_VACK = 4;
 literal CC$C_EVT_DONE = 5;
*5D
 literal CC$C_EVT_TRANS = 6;
 literal CC$C_EVT_SHORT_MSG = 7;
 literal CC$C_EVT_BAD_ECO = 8;
 literal CC$C_EVT_HS_TMO = 9;
 literal CC$C_EVT_LISTEN_TMO = 10;
 literal CC$C_EVT_AUTHORIZE = 11;
 literal CC$C_EVT_BAD_MC = 12;
*5E
*5I
 literal CC$C_EVT_SOLICIT_SRV = 6;
 literal CC$C_EVT_TRANS = 7;
 literal CC$C_EVT_SHORT_MSG = 8;
 literal CC$C_EVT_BAD_ECO = 9;
 literal CC$C_EVT_HS_TMO = 10;
 literal CC$C_EVT_LISTEN_TMO = 11;
 literal CC$C_EVT_AUTHORIZE = 12;
 literal CC$C_EVT_BAD_MC = 13;
*5E
 literal CC$C_STATE_CLOSED = 0;
 literal CC$C_STATE_CCSTART_SENT = 1;
 literal CC$C_STATE_CCSTART_REC = 2;
*5D
 literal CC$C_STATE_OPEN = 3;
*5E
*5I
 literal CC$C_STATE_SOLICIT_REC = 3;
 literal CC$C_STATE_OPEN = 4;
 literal CC$C_STATE_resv1 = 5;
 literal CC$C_STATE_resv2 = 6;
 literal CC$C_STATE_resv3 = 7;
 literal CC$C_STATE_TOTAL = 8;
*5E
 literal CC$S_CCDEF = 4;
 macro CC$L_DUMMY = 0,0,32,0 %;
  
*2D
 !*** MODULE $PEERLDEF ***
*2E
*2I
*3D
 !*** MODULE PEERL ***
*3E
*3I
*4D
 !*** MODULE $PEERLDEF ***
*4E
*4I
 !*** MODULE PEERL ***
*4E
*3E
*2E
 literal PEERL$C_LENGTH = 64;
 literal PEERL$C_PEM_LENGTH = 62;
 literal PEERL$C_TOTAL_LONGWORDS = 14;
 literal PEERL$S_PEERLDEF = 64;
 macro PEERL$W_SCS_PAD = 0,0,16,0 %;
 macro PEERL$W_REGSAV_SIZE = 2,0,16,0 %;
 macro PEERL$W_MBZ = 4,0,16,0 %;
 macro PEERL$B_ERROR_SUBTYPE = 6,0,8,0 %;
 macro PEERL$B_ERROR_TYPE = 7,0,8,0 %;
 macro PEERL$L_IOSB1 = 8,0,32,0 %;
 macro PEERL$L_IOSB2 = 12,0,32,0 %;
 macro PEERL$T_DL_DEVNAM = 16,0,0,0 %;
 literal PEERL$S_DL_DEVNAM = 16;
 macro PEERL$T_DST_NODENAME = 32,0,0,0 %;
 literal PEERL$S_DST_NODENAME = 16;
 macro PEERL$L_DST_ADDR_LO = 48,0,32,0 %;
 macro PEERL$W_DST_ADDR_HI = 52,0,16,0 %;
 macro PEERL$L_LOCAL_ADDR_LO = 54,0,32,0 %;
 macro PEERL$W_LOCAL_ADDR_HI = 58,0,16,0 %;
 macro PEERL$W_ERROR_COUNT = 60,0,16,0 %;
 macro PEERL$W_DL_UNIT = 62,0,16,0 %;